diff options
| -rw-r--r-- | rtl/core/control/ldst/ldst.sv | 8 | ||||
| -rw-r--r-- | rtl/core/control/writeback.sv | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv index 0e0a39c..57f8edc 100644 --- a/rtl/core/control/ldst/ldst.sv +++ b/rtl/core/control/ldst/ldst.sv @@ -8,7 +8,6 @@ module core_control_ldst input insn_decode dec, input logic issue, mem_ready, - mem_ex_fail, input word rd_value_b, q_alu, q_shifter, @@ -43,10 +42,7 @@ module core_control_ldst assign popped = increment ? popped_lower : popped_upper; assign ldst_next = !cycle.transfer || mem_ready; - assign mem_data_wr = q_shifter; - - //TODO - assign mem_ex_lock = 0; + assign mem_data_wr = mem_ex_lock ? alu_b : q_shifter; core_control_ldst_pop pop ( @@ -83,6 +79,7 @@ module core_control_ldst mem_write <= 0; mem_start <= 0; mem_offset <= 0; + mem_ex_lock <= 0; end else begin if(mem_start) mem_start <= 0; @@ -101,6 +98,7 @@ module core_control_ldst mem_regs <= dec.ldst.regs; mem_write <= !dec.ldst.load; + mem_ex_lock <= dec.ldst.exclusive; end else if(next_cycle.transfer) begin if(!cycle.transfer) begin ldst <= 0; diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index a7738fb..50e780d 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -10,6 +10,8 @@ module core_control_writeback input word q_alu, ldst_read, input logic mem_ready, + mem_ex_fail, + mem_ex_lock, mem_write, input word mul_q_hi, mul_q_lo, @@ -62,7 +64,7 @@ module core_control_writeback writeback = 0; if(cycle.transfer) - wr_value = ldst_read; + wr_value = (mem_ex_lock && mem_write) ? {31'd0, mem_ex_fail} : ldst_read; else if(cycle.base_writeback) wr_value = saved_base; else if(cycle.mul || cycle.mul_hi_wb) |