diff options
| -rw-r--r-- | gfx_hw.tcl | 1 | ||||
| -rw-r--r-- | rtl/gfx/gfx.sv | 15 | ||||
| -rw-r--r-- | rtl/gfx/gfx_clear.sv | 70 | ||||
| -rw-r--r-- | rtl/gfx/gfx_cmd.sv | 15 |
4 files changed, 94 insertions, 7 deletions
@@ -67,6 +67,7 @@ add_fileset_file gfx_setup_offsets.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_setup_offs add_fileset_file gfx_raster.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_raster.sv add_fileset_file gfx_raster_fine.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_raster_fine.sv add_fileset_file gfx_raster_coarse.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_raster_coarse.sv +add_fileset_file gfx_clear.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_clear.sv # diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv index fcaaffb..f973b73 100644 --- a/rtl/gfx/gfx.sv +++ b/rtl/gfx/gfx.sv @@ -26,7 +26,7 @@ module gfx output rgb30 scan_data ); - logic enable_clear, swap_buffers; + logic enable_clear, start_clear, swap_buffers; rgb24 clear_color; gfx_cmd cmd @@ -38,10 +38,17 @@ module gfx gfx_masks masks ( - .frag_mask_set(0), - .frag_mask_write(0), .frag_mask_read_addr(), - .frag_mask_write_addr(), + .* + ); + + logic frag_mask_set, frag_mask_write, frag_wait; + linear_coord frag_mask_write_addr; + + gfx_clear clear + ( + .rop_mask_addr(), + .rop_mask_assert(0), .* ); diff --git a/rtl/gfx/gfx_clear.sv b/rtl/gfx/gfx_clear.sv new file mode 100644 index 0000000..ae9a20c --- /dev/null +++ b/rtl/gfx/gfx_clear.sv @@ -0,0 +1,70 @@ +`include "gfx/gfx_defs.sv" + +module gfx_clear +( + input logic clk, + rst_n, + + input logic start_clear, + + input linear_coord rop_mask_addr, + input logic rop_mask_assert, + output logic frag_wait, + + output logic frag_mask_set, + frag_mask_write, + output linear_coord frag_mask_write_addr +); + + enum int unsigned + { + FRAG, + CLEAR + } state; + + logic end_clear; + + assign end_clear = frag_mask_write_addr == `GFX_LINEAR_RES - 1; + + always_comb + unique case (state) + FRAG: frag_wait = start_clear; + CLEAR: frag_wait = 1; + endcase + + always_ff @(posedge clk or negedge rst_n) + if (!rst_n) begin + state <= FRAG; + frag_mask_write <= 0; + end else unique case (state) + FRAG: begin + frag_mask_write <= rop_mask_assert; + + if (start_clear) begin + state <= CLEAR; + frag_mask_write <= 1; + end + end + + CLEAR: + if (end_clear) begin + state <= FRAG; + frag_mask_write <= 0; + end + endcase + + always_ff @(posedge clk) + unique case (state) + FRAG: begin + frag_mask_set <= !start_clear; + frag_mask_write_addr <= rop_mask_addr; + + if (start_clear) + frag_mask_write_addr <= 0; + end + + CLEAR: + frag_mask_write_addr <= frag_mask_write_addr + 1; + endcase + +endmodule diff --git a/rtl/gfx/gfx_cmd.sv b/rtl/gfx/gfx_cmd.sv index 424cf5d..98845c9 100644 --- a/rtl/gfx/gfx_cmd.sv +++ b/rtl/gfx/gfx_cmd.sv @@ -15,13 +15,15 @@ module gfx_cmd output logic swap_buffers, enable_clear, + start_clear, output rgb24 clear_color ); struct packed { - logic[5:0] mbz; - logic enable_clear, + logic[4:0] mbz; + logic start_frame, + enable_clear, swap_buffers; rgb24 clear_color; } readdata_scan, writedata_scan; @@ -36,17 +38,21 @@ module gfx_cmd assign cmd_readdata = readdata_scan; rgb24 next_clear_color; - logic next_enable_clear, next_swap_buffers; + logic next_start_clear, next_enable_clear, next_swap_buffers; always_ff @(posedge clk or negedge rst_n) if (!rst_n) begin + start_clear <= 0; enable_clear <= 0; swap_buffers <= 0; + next_start_clear <= 0; next_enable_clear <= 0; next_swap_buffers <= 0; end else begin + start_clear <= 0; if (vsync) begin + start_clear <= next_start_clear; enable_clear <= next_enable_clear; swap_buffers <= next_swap_buffers; end @@ -54,6 +60,9 @@ module gfx_cmd if (cmd_write) begin next_enable_clear <= writedata_scan.enable_clear; next_swap_buffers <= writedata_scan.swap_buffers; + + if (!next_start_clear) + next_start_clear <= writedata_scan.start_frame && writedata_scan.enable_clear; end end |