diff options
| -rw-r--r-- | rtl/core/fetch/fetch.sv | 9 | ||||
| -rw-r--r-- | rtl/core/mmu/mmu.sv | 2 |
2 files changed, 8 insertions, 3 deletions
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv index 1853ee0..63cb936 100644 --- a/rtl/core/fetch/fetch.sv +++ b/rtl/core/fetch/fetch.sv @@ -23,16 +23,19 @@ module core_fetch ); ptr next_pc, hold_addr, target; - logic fetched_valid, discard; + logic prefetch_ready, fetched_valid, discard, pending, next_pending; + assign fetch = prefetch_ready && !discard; assign flush = branch || prefetch_flush; assign target = wr_pc ? wr_current[31:2] : branch_target; //TODO: alignment exception + assign next_pending = fetch || (pending && !fetched); assign fetched_valid = fetched && !discard; core_prefetch #(.ORDER(PREFETCH_ORDER)) prefetch ( .head(fetch_head), .fetched(fetched_valid), + .fetch(prefetch_ready), .* ); @@ -54,10 +57,12 @@ module core_fetch always_ff @(posedge clk or negedge rst_n) if(!rst_n) begin + pending <= 0; discard <= 0; hold_addr <= 0; end else begin - discard <= discard ? !fetched : flush && fetch; + pending <= next_pending; + discard <= next_pending && (discard || flush); hold_addr <= addr; end diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv index cfb223f..51d7f32 100644 --- a/rtl/core/mmu/mmu.sv +++ b/rtl/core/mmu/mmu.sv @@ -28,9 +28,9 @@ module core_mmu DATA } master, next_master; - logic active, hold_start, hold_write, hold_issue, hold_free, transition; ptr hold_addr; word hold_data_wr; + logic active, hold_start, hold_write, hold_issue, hold_free, transition; //TODO assign insn_data_rd = bus_data_rd; |