diff options
| -rw-r--r-- | rtl/core/arm810.sv | 3 | ||||
| -rw-r--r-- | rtl/core/cycles.sv | 18 | ||||
| -rw-r--r-- | rtl/core/psr.sv | 5 | ||||
| -rw-r--r-- | rtl/core/regs/file.sv | 11 |
4 files changed, 20 insertions, 17 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 5ba1a11..8ea6ed3 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -35,7 +35,6 @@ module arm810 core_decode decode ( - .flags(next_flags), .execute(dec_execute), .undefined(dec_undefined), .writeback(dec_writeback), @@ -61,7 +60,7 @@ module arm810 .* ); - psr_flags flags, next_flags; + psr_flags flags; core_psr psr ( diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv index 1524883..8945bc2 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/cycles.sv @@ -37,10 +37,11 @@ module core_cycles logic final_writeback, data_snd_is_imm, data_snd_shift_by_reg; logic[5:0] data_shift_imm; logic[7:0] data_imm; + logic bubble; word saved_base; reg_num r_shift; - assign stall = next_cycle != EXECUTE; + assign stall = (next_cycle != EXECUTE) | bubble; assign pc_visible = pc + 2; assign reg_mode = `MODE_SVC; //TODO @@ -49,6 +50,9 @@ module core_cycles if((cycle == EXECUTE) & data_snd_shift_by_reg) next_cycle = RD_SHIFT; + if(bubble) + next_cycle = EXECUTE; + unique case(cycle) RD_SHIFT: alu_base = saved_base; @@ -68,15 +72,20 @@ module core_cycles always_ff @(posedge clk) begin cycle <= next_cycle; + bubble <= 0; unique case(next_cycle) EXECUTE: begin branch <= 0; update_flags <= 0; - branch_target <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + branch_target <= {30{1'bx}}; final_writeback <= 0; - if(dec_execute) begin + if(dec_execute & ~bubble) begin + bubble <= + (dec_update_flags & update_flags) + | (final_writeback & ((rd == dec_alu.rn) | (rd == dec_alu.r_snd))); + branch <= dec_branch; final_writeback <= dec_writeback; update_flags <= dec_update_flags; @@ -115,12 +124,13 @@ module core_cycles initial begin cycle = EXECUTE; + bubble = 0; + pc = 0; branch = 1; writeback = 0; data_snd_shift_by_reg = 0; branch_target = 30'd0; - pc = 0; end endmodule diff --git a/rtl/core/psr.sv b/rtl/core/psr.sv index 2c0d48f..bc682c1 100644 --- a/rtl/core/psr.sv +++ b/rtl/core/psr.sv @@ -7,10 +7,11 @@ module core_psr alu_v_valid, input psr_flags alu_flags, - output psr_flags flags, - next_flags + output psr_flags flags ); + psr_flags next_flags; + always_comb begin next_flags = flags; diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index b2dd634..22f7ccf 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -13,19 +13,12 @@ module core_reg_file // Ver comentario en uarch.sv word file[30]; - word q, wr_value_hold; - logic overwrite_hold; - - assign rd_value = overwrite_hold ? wr_value_hold : q; always @(negedge clk) begin - if(wr_enable) begin + if(wr_enable) file[wr_index] <= wr_value; - wr_value_hold <= wr_value; - end - q <= file[rd_index]; - overwrite_hold <= wr_enable & (rd_index == wr_index); + rd_value <= file[rd_index]; end endmodule |