diff options
| -rw-r--r-- | rtl/top/conspiracion.sv | 8 | ||||
| -rw-r--r-- | tb/platform.sv | 49 | ||||
| -rw-r--r-- | tb/top/conspiracion.cpp | 42 |
3 files changed, 89 insertions, 10 deletions
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 83e7d10..174dceb 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -48,10 +48,10 @@ module conspiracion ); initial begin - addr <= 0; - start <= 0; - state <= IDLE; - done <= 0; + addr = 0; + start = 0; + state = IDLE; + done = 0; end assign data_rw[7:0] = out; diff --git a/tb/platform.sv b/tb/platform.sv new file mode 100644 index 0000000..10df2e0 --- /dev/null +++ b/tb/platform.sv @@ -0,0 +1,49 @@ +module platform ( + input wire clk_clk, // clk.clk + input wire [29:0] master_0_core_addr /*verilator public*/,// master_0_core.addr + output wire [31:0] master_0_core_data_rd /*verilator public*/,// .data_rd + input wire [31:0] master_0_core_data_rw /*verilator public*/,// .data_rw + output wire master_0_core_ready /*verilator public*/,// .ready + input wire master_0_core_write /*verilator public*/,// .write + input wire master_0_core_start /*verilator public*/,// .start + output wire [12:0] memory_mem_a, // memory.mem_a + output wire [2:0] memory_mem_ba, // .mem_ba + output wire memory_mem_ck, // .mem_ck + output wire memory_mem_ck_n, // .mem_ck_n + output wire memory_mem_cke, // .mem_cke + output wire memory_mem_cs_n, // .mem_cs_n + output wire memory_mem_ras_n, // .mem_ras_n + output wire memory_mem_cas_n, // .mem_cas_n + output wire memory_mem_we_n, // .mem_we_n + output wire memory_mem_reset_n, // .mem_reset_n + inout wire [7:0] memory_mem_dq, // .mem_dq + inout wire memory_mem_dqs, // .mem_dqs + inout wire memory_mem_dqs_n, // .mem_dqs_n + output wire memory_mem_odt, // .mem_odt + output wire memory_mem_dm, // .mem_dm + input wire memory_oct_rzqin, // .oct_rzqin + input wire reset_reset_n // reset.reset_n + ); + + logic[31:0] avl_address /*verilator public*/; + logic avl_read /*verilator public*/; + logic avl_write /*verilator public*/; + logic[31:0] avl_readdata /*verilator public*/; + logic[31:0] avl_writedata /*verilator public*/; + logic avl_waitrequest /*verilator public*/; + logic[3:0] avl_byteenable /*verilator public*/; + + bus_master master_0 + ( + .clk(clk_clk), + .rst(!reset_reset_n), + .addr(master_0_core_addr), + .start(master_0_core_start), + .write(master_0_core_write), + .ready(master_0_core_ready), + .data_rd(master_0_core_data_rd), + .data_rw(master_0_core_data_rw), + .* + ); + +endmodule diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp index d4bdbcb..b8f803c 100644 --- a/tb/top/conspiracion.cpp +++ b/tb/top/conspiracion.cpp @@ -2,18 +2,48 @@ #include <cstdio> #include "Vconspiracion.h" +#include "Vconspiracion_conspiracion.h" +#include "Vconspiracion_platform.h" + +#include "../avalon.hpp" int main(int argc, char **argv) { - Verilated::commandArgs(argc, argv); // Remember args - Verilated::traceEverOn(true); + using namespace taller::avalon; + + Verilated::commandArgs(argc, argv); Vconspiracion top; - // Do not instead make Vtop as a file-scope static - // variable, as the "C++ static initialization order fiasco" - // may cause a crash + interconnect<Vconspiracion_platform> avl(*top.conspiracion->plat); + + int time = 0; + auto tick = [&]() + { + top.clk_clk = 0; + top.eval(); + top.clk_clk = 1; + top.eval(); + avl.tick(); + + std::printf("[%02d] out=0x%02x, done=%d\n", ++time, top.out, top.done); + }; + + top.dir = 1; + top.io = 1; + top.mov = 1; + top.clr = 1; + + for(int i = 0; i < 5; ++i) + { + top.add = 0; + tick(); + top.add = 1; + tick(); + } - top.eval(); + top.io = 0; + tick(); + tick(); top.final(); } |