diff options
Diffstat (limited to '')
| -rw-r--r-- | platform.qsys | 4 | ||||
| -rw-r--r-- | rtl/top/conspiracion.sv | 1 | ||||
| -rw-r--r-- | tb/platform.sv | 1 |
3 files changed, 4 insertions, 2 deletions
diff --git a/platform.qsys b/platform.qsys index 5ed2a73..cc69a64 100644 --- a/platform.qsys +++ b/platform.qsys @@ -168,6 +168,7 @@ internal="pll_0.outclk3" type="clock" dir="start" /> + <interface name="pll_0_reset" internal="pll_0.reset" type="reset" dir="end" /> <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> <interface name="vga_controller_0_dac" @@ -953,7 +954,7 @@ <parameter name="gui_phase_shift_deg8" value="0.0" /> <parameter name="gui_phase_shift_deg9" value="0.0" /> <parameter name="gui_phout_division" value="1" /> - <parameter name="gui_pll_auto_reset" value="Off" /> + <parameter name="gui_pll_auto_reset" value="On" /> <parameter name="gui_pll_bandwidth_preset" value="Auto" /> <parameter name="gui_pll_cascading_mode">Create an adjpllin signal to connect with an upstream PLL</parameter> <parameter name="gui_pll_mode" value="Fractional-N PLL" /> @@ -1146,7 +1147,6 @@ version="20.1" start="clk_0.clk_reset" end="address_span_extender_0.reset" /> - <connection kind="reset" version="20.1" start="clk_0.clk_reset" end="pll_0.reset" /> <connection kind="reset" version="20.1" start="clk_0.clk_reset" end="vram.reset" /> <connection kind="reset" diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 6d8784f..4409d9b 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -66,6 +66,7 @@ module conspiracion .master_0_core_write(write), .master_0_core_start(start), .master_0_core_irq(irq), + .pll_0_reset_reset(0), //TODO: reset controller, algún día .pll_0_outclk3_clk(vram_wire_clk), .pio_0_external_connection_export(pio_leds), .* diff --git a/tb/platform.sv b/tb/platform.sv index a43af19..21fb45b 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -29,6 +29,7 @@ module platform output wire memory_mem_dm, // .mem_dm input wire memory_oct_rzqin, // .oct_rzqin output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export + input wire pll_0_reset_reset, output wire pll_0_outclk3_clk, // pll_0_outclk3.clk input wire reset_reset_n /*verilator public*/,// reset.reset_n output wire [12:0] vram_wire_addr, // vram_wire.addr |