diff options
Diffstat (limited to '')
| -rw-r--r-- | conspiracion_bus_master_hw.tcl | 138 | ||||
| -rw-r--r-- | platform.qsys | 58 | ||||
| -rw-r--r-- | rtl/bus/master.sv | 58 | ||||
| -rw-r--r-- | rtl/conspiracion.sv | 17 |
4 files changed, 270 insertions, 1 deletions
diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl new file mode 100644 index 0000000..81b62d0 --- /dev/null +++ b/conspiracion_bus_master_hw.tcl @@ -0,0 +1,138 @@ +# TCL File Generated by Component Editor 20.1 +# Sun Sep 04 22:05:36 GMT 2022 +# DO NOT MODIFY + + +# +# conspiracion_bus_master "Toplevel bus master" v1.0 +# 2022.09.04.22:05:36 +# +# + +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module conspiracion_bus_master +# +set_module_property DESCRIPTION "" +set_module_property NAME conspiracion_bus_master +set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME "Toplevel bus master" +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL bus_master +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file master.sv SYSTEM_VERILOG PATH rtl/bus/master.sv TOP_LEVEL_FILE + + +# +# parameters +# + + +# +# display items +# + + +# +# connection point clock +# +add_interface clock clock end +set_interface_property clock clockRate 0 +set_interface_property clock ENABLED true +set_interface_property clock EXPORT_OF "" +set_interface_property clock PORT_NAME_MAP "" +set_interface_property clock CMSIS_SVD_VARIABLES "" +set_interface_property clock SVD_ADDRESS_GROUP "" + +add_interface_port clock clk clk Input 1 + + +# +# connection point avalon_master +# +add_interface avalon_master avalon start +set_interface_property avalon_master addressUnits SYMBOLS +set_interface_property avalon_master associatedClock clock +set_interface_property avalon_master associatedReset reset_sink +set_interface_property avalon_master bitsPerSymbol 8 +set_interface_property avalon_master burstOnBurstBoundariesOnly false +set_interface_property avalon_master burstcountUnits WORDS +set_interface_property avalon_master doStreamReads false +set_interface_property avalon_master doStreamWrites false +set_interface_property avalon_master holdTime 0 +set_interface_property avalon_master linewrapBursts false +set_interface_property avalon_master maximumPendingReadTransactions 0 +set_interface_property avalon_master maximumPendingWriteTransactions 0 +set_interface_property avalon_master readLatency 0 +set_interface_property avalon_master readWaitTime 1 +set_interface_property avalon_master setupTime 0 +set_interface_property avalon_master timingUnits Cycles +set_interface_property avalon_master writeWaitTime 0 +set_interface_property avalon_master ENABLED true +set_interface_property avalon_master EXPORT_OF "" +set_interface_property avalon_master PORT_NAME_MAP "" +set_interface_property avalon_master CMSIS_SVD_VARIABLES "" +set_interface_property avalon_master SVD_ADDRESS_GROUP "" + +add_interface_port avalon_master avl_address address Output 32 +add_interface_port avalon_master avl_read read Output 1 +add_interface_port avalon_master avl_readdata readdata Input 32 +add_interface_port avalon_master avl_write write Output 1 +add_interface_port avalon_master avl_writedata writedata Output 32 +add_interface_port avalon_master avl_byteenable byteenable Output 4 +add_interface_port avalon_master avl_waitrequest waitrequest Input 1 + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clock +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink rst reset Input 1 + + +# +# connection point core +# +add_interface core conduit end +set_interface_property core associatedClock clock +set_interface_property core associatedReset reset_sink +set_interface_property core ENABLED true +set_interface_property core EXPORT_OF "" +set_interface_property core PORT_NAME_MAP "" +set_interface_property core CMSIS_SVD_VARIABLES "" +set_interface_property core SVD_ADDRESS_GROUP "" + +add_interface_port core addr addr Input 30 +add_interface_port core data_rd data_rd Output 32 +add_interface_port core data_rw data_rw Input 32 +add_interface_port core ready ready Output 1 +add_interface_port core write write Input 1 +add_interface_port core start start Input 1 + diff --git a/platform.qsys b/platform.qsys index d2fa081..d9ab17c 100644 --- a/platform.qsys +++ b/platform.qsys @@ -25,6 +25,38 @@ type = "int"; } } + element master_0 + { + datum _sortIndex + { + value = "2"; + type = "int"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } + element platform + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } } ]]></parameter> <parameter name="clockCrossingAdapter" value="HANDSHAKE" /> @@ -47,6 +79,12 @@ <parameter name="useTestBenchNamingPattern" value="false" /> <instanceScript></instanceScript> <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" /> + <interface name="master_0_conduit_end" internal="master_0.conduit_end" /> + <interface + name="master_0_core" + internal="master_0.core" + type="conduit" + dir="end" /> <interface name="memory" internal="hps_0.memory" type="conduit" dir="end" /> <interface name="reset" internal="clk_0.clk_in_reset" type="reset" dir="end" /> <module name="clk_0" kind="clock_source" version="20.1" enabled="1"> @@ -585,11 +623,31 @@ <parameter name="usb_mp_clk_div" value="0" /> <parameter name="use_default_mpu_clk" value="true" /> </module> + <module + name="master_0" + kind="conspiracion_bus_master" + version="1.0" + enabled="1" /> + <connection + kind="avalon" + version="20.1" + start="master_0.avalon_master" + end="hps_0.f2h_sdram0_data"> + <parameter name="arbitrationPriority" value="1" /> + <parameter name="baseAddress" value="0x0000" /> + <parameter name="defaultConnection" value="false" /> + </connection> + <connection kind="clock" version="20.1" start="clk_0.clk" end="master_0.clock" /> <connection kind="clock" version="20.1" start="clk_0.clk" end="hps_0.f2h_sdram0_clock" /> + <connection + kind="reset" + version="20.1" + start="clk_0.clk_reset" + end="master_0.reset_sink" /> <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" /> <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" /> <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" /> diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv new file mode 100644 index 0000000..63ea2be --- /dev/null +++ b/rtl/bus/master.sv @@ -0,0 +1,58 @@ +module bus_master +( + input logic clk, + rst, + + input logic[29:0] addr, + input logic start, + write, + output logic ready, + output logic[31:0] data_rd, + input logic[31:0] data_rw, + + output logic[31:0] avl_address, + output logic avl_read, + avl_write, + input logic[31:0] avl_readdata, + output logic[31:0] avl_writedata, + input logic avl_waitrequest, + output logic[3:0] avl_byteenable +); + + enum { + REQUEST, + WAIT, + RESPONSE + } state; + + assign data_rd = avl_readdata; + + always_ff @(posedge clk) unique case(state) + REQUEST: if(start) begin + avl_address <= {addr, 2'b00}; + avl_read <= ~write; + avl_write <= write; + avl_writedata <= data_rw; + end + + WAIT: if(~avl_waitrequest) begin + ready <= 1; + state <= RESPONSE; + end + + RESPONSE: begin + ready <= 0; + avl_read <= 0; + avl_write <= 0; + state <= REQUEST; + end + endcase + + initial begin + ready <= 0; + avl_read <= 0; + avl_write <= 0; + state <= REQUEST; + end + +endmodule diff --git a/rtl/conspiracion.sv b/rtl/conspiracion.sv index 0b652e7..96c6fb8 100644 --- a/rtl/conspiracion.sv +++ b/rtl/conspiracion.sv @@ -20,6 +20,21 @@ module conspiracion input wire reset_reset_n // reset.reset_n ); - platform plat(.*); + logic[29:0] addr; + logic[31:0] data_rd, data_rw; + logic ready, write, start; + + platform plat + ( + .master_0_core_addr(addr), + .master_0_core_data_rd(data_rd), + .master_0_core_data_rw(data_rw), + .master_0_core_ready(ready), + .master_0_core_write(write), + .master_0_core_start(start), + .* + ); + + initial start <= 0; endmodule |