10 files changed, 12 insertions, 12 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf
index 4852eeb..7945383 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -142,6 +142,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/isa.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/addr.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/misc.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/multiple.sv
@@ -149,7 +150,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/single.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/snd.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv
@@ -252,4 +252,4 @@ set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_reset
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to memory_mem_reset_n -tag __hps_sdram_p0
 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dm -tag __hps_sdram_p0
 set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to memory_mem_dm -tag __hps_sdram_p0
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-\ No newline at end of file
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/rtl/core/decode/branch.sv b/rtl/core/decode/branch.sv
index 9916374..1dbc1ad 100644
--- a/rtl/core/decode/branch.sv
+++ b/rtl/core/decode/branch.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_branch
diff --git a/rtl/core/decode/conds.sv b/rtl/core/decode/conds.sv
index 564ed27..60922a0 100644
--- a/rtl/core/decode/conds.sv
+++ b/rtl/core/decode/conds.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_conds
diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data.sv
index e2a44df..cb21f5e 100644
--- a/rtl/core/decode/data.sv
+++ b/rtl/core/decode/data.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_data
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 73d3b59..5e72afe 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode
diff --git a/rtl/core/isa.sv b/rtl/core/decode/isa.sv
index c98cfd9..baaf371 100644
--- a/rtl/core/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -1,5 +1,5 @@
-`ifndef CORE_ISA_SV
-`define CORE_ISA_SV
+`ifndef CORE_DECODE_ISA_SV
+`define CORE_DECODE_ISA_SV
 
 `define FIELD_COND [31:28]
 `define FIELD_OP   [27:0]
diff --git a/rtl/core/decode/ldst/misc.sv b/rtl/core/decode/ldst/misc.sv
index f2fe258..d8ac898 100644
--- a/rtl/core/decode/ldst/misc.sv
+++ b/rtl/core/decode/ldst/misc.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_misc
diff --git a/rtl/core/decode/ldst/multiple.sv b/rtl/core/decode/ldst/multiple.sv
index d286a67..201f333 100644
--- a/rtl/core/decode/ldst/multiple.sv
+++ b/rtl/core/decode/ldst/multiple.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_multiple
diff --git a/rtl/core/decode/ldst/single.sv b/rtl/core/decode/ldst/single.sv
index 0665178..402c17b 100644
--- a/rtl/core/decode/ldst/single.sv
+++ b/rtl/core/decode/ldst/single.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_ldst_single
diff --git a/rtl/core/decode/snd.sv b/rtl/core/decode/snd.sv
index 4dbb028..4e8de96 100644
--- a/rtl/core/decode/snd.sv
+++ b/rtl/core/decode/snd.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
 module core_decode_snd