4 files changed, 37 insertions, 39 deletions
diff --git a/rtl/gfx/gfx_fp_add.sv b/rtl/gfx/gfx_fp_add.sv
index 6ba7b1c..0b3058a 100644
--- a/rtl/gfx/gfx_fp_add.sv
+++ b/rtl/gfx/gfx_fp_add.sv
@@ -19,22 +19,23 @@ module gfx_fp_add
 		.*
 	);
 `else
-	fp a_pipeline[`FP_ADD_STAGES - 1], b_pipeline[`FP_ADD_STAGES - 1];
+	fp a_pop, b_pop;
 
-	integer i;
+	assign q = $c("taller::fp_add(", a_pop, ", ", b_pop, ")");
 
-	always_ff @(posedge clk)
-		if (!stall) begin
-			a_pipeline[0] <= a;
-			b_pipeline[0] <= b;
-
-			for (i = 1; i < `FP_ADD_STAGES - 1; ++i) begin
-				a_pipeline[i] <= a_pipeline[i - 1];
-				b_pipeline[i] <= b_pipeline[i - 1];
-			end
+	gfx_pipes #(.WIDTH($bits(a)), .DEPTH(`FP_ADD_STAGES)) a_pipes
+	(
+		.in(a),
+		.out(a_pop),
+		.*
+	);
 
-			q <= $c("taller::fp_add(", a_pipeline[`FP_ADD_STAGES - 2], ", ", b_pipeline[`FP_ADD_STAGES - 2], ")");
-		end
+	gfx_pipes #(.WIDTH($bits(b)), .DEPTH(`FP_ADD_STAGES)) b_pipes
+	(
+		.in(b),
+		.out(b_pop),
+		.*
+	);
 `endif
 
 endmodule
diff --git a/rtl/gfx/gfx_fp_inv.sv b/rtl/gfx/gfx_fp_inv.sv
index 41b3ad5..33f7bf8 100644
--- a/rtl/gfx/gfx_fp_inv.sv
+++ b/rtl/gfx/gfx_fp_inv.sv
@@ -18,19 +18,16 @@ module gfx_fp_inv
 		.*
 	);
 `else
-	fp pipeline[`FP_INV_STAGES - 1];
+	fp a_pop;
 
-	integer i;
+	assign q = $c("taller::fp_inv(", a_pop, ")");
 
-	always_ff @(posedge clk)
-		if (!stall) begin
-			pipeline[0] <= a;
-
-			for (i = 1; i < `FP_INV_STAGES - 1; ++i)
-				pipeline[i] <= pipeline[i - 1];
-
-			q <= $c("taller::fp_inv(", pipeline[`FP_INV_STAGES - 2], ")");
-		end
+	gfx_pipes #(.WIDTH($bits(a)), .DEPTH(`FP_INV_STAGES)) a_pipes
+	(
+		.in(a),
+		.out(a_pop),
+		.*
+	);
 `endif
 
 endmodule
diff --git a/rtl/gfx/gfx_fp_mul.sv b/rtl/gfx/gfx_fp_mul.sv
index eb7d7d7..7ff3c02 100644
--- a/rtl/gfx/gfx_fp_mul.sv
+++ b/rtl/gfx/gfx_fp_mul.sv
@@ -19,22 +19,23 @@ module gfx_fp_mul
 		.*
 	);
 `else
-	fp a_pipeline[`FP_MUL_STAGES - 1], b_pipeline[`FP_MUL_STAGES - 1];
+	fp a_pop, b_pop;
 
-	integer i;
+	assign q = $c("taller::fp_mul(", a_pop, ", ", b_pop, ")");
 
-	always_ff @(posedge clk)
-		if (!stall) begin
-			a_pipeline[0] <= a;
-			b_pipeline[0] <= b;
-
-			for (i = 1; i < `FP_MUL_STAGES - 1; ++i) begin
-				a_pipeline[i] <= a_pipeline[i - 1];
-				b_pipeline[i] <= b_pipeline[i - 1];
-			end
+	gfx_pipes #(.WIDTH($bits(a)), .DEPTH(`FP_MUL_STAGES)) a_pipes
+	(
+		.in(a),
+		.out(a_pop),
+		.*
+	);
 
-			q <= $c("taller::fp_mul(", a_pipeline[`FP_MUL_STAGES - 2], ", ", b_pipeline[`FP_MUL_STAGES - 2], ")");
-		end
+	gfx_pipes #(.WIDTH($bits(b)), .DEPTH(`FP_MUL_STAGES)) b_pipes
+	(
+		.in(b),
+		.out(b_pop),
+		.*
+	);
 `endif
 
 endmodule
diff --git a/rtl/gfx/gfx_pipes.sv b/rtl/gfx/gfx_pipes.sv
index 55ebd19..09b1d43 100644
--- a/rtl/gfx/gfx_pipes.sv
+++ b/rtl/gfx/gfx_pipes.sv
@@ -13,12 +13,11 @@ module gfx_pipes
 
 	assign out = pipes[DEPTH - 1];
 
-	integer i;
 	always_ff @(posedge clk)
 		if (!stall) begin
 			pipes[0] <= in;
 
-			for (i = 1; i < DEPTH; ++i)
+			for (integer i = 1; i < DEPTH; ++i)
 				pipes[i] <= pipes[i - 1];
 		end