diff options
Diffstat (limited to '')
| -rw-r--r-- | rtl/core/control/select.sv | 4 | ||||
| -rw-r--r-- | tb/sim/shifts.S | 3 | ||||
| -rw-r--r-- | tb/sim/shifts.py | 1 |
3 files changed, 7 insertions, 1 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index 1ea2c31..0ab7bb2 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -29,7 +29,9 @@ module core_control_select if(next_cycle.issue) begin ra = dec.data.rn; rb = dec.snd.r; - end else if(next_cycle.transfer) begin + end else if(next_cycle.rd_indirect_shift) + rb = r_shift; + else if(next_cycle.transfer) begin if(ldst_next) // final_rd viene de dec.ldst.rd rb = pop_valid ? popped : final_rd; diff --git a/tb/sim/shifts.S b/tb/sim/shifts.S index 68ef3f8..6209157 100644 --- a/tb/sim/shifts.S +++ b/tb/sim/shifts.S @@ -14,4 +14,7 @@ reset: # tmp = 0 # r2 = r0 = 00015000 eor r2, r0, r2, asr #7 + ldr r4, =(512 << 20) + ldr r5, =#60 + lsr r4, r4, r5 mov pc, lr diff --git a/tb/sim/shifts.py b/tb/sim/shifts.py index 38f24a2..9923124 100644 --- a/tb/sim/shifts.py +++ b/tb/sim/shifts.py @@ -2,3 +2,4 @@ def final(): assert_reg(r0, 0x00015000) assert_reg(r2, 0x00015000) assert_reg(r3, 0xaaa9fd55) + assert_reg(r4, 0) |