diff options
Diffstat (limited to '')
| -rw-r--r-- | rtl/cache/control.sv | 8 | ||||
| -rw-r--r-- | rtl/cache/routing.sv | 2 | ||||
| -rw-r--r-- | tb/avalon.hpp | 4 | ||||
| -rw-r--r-- | tb/sim/fibonacci.py | 2 |
4 files changed, 9 insertions, 7 deletions
diff --git a/rtl/cache/control.sv b/rtl/cache/control.sv index a930e87..73eb644 100644 --- a/rtl/cache/control.sv +++ b/rtl/cache/control.sv @@ -84,13 +84,13 @@ module cache_control assign may_send = may_send_if_token_held && in_token_valid; assign may_send_if_token_held - = (!in_token.e2.valid || in_token.e2.index != core_index || in_token.e2.tag != core_tag) - && (!in_token.e1.valid || in_token.e1.index != core_index || in_token.e1.tag != core_tag) - && (!in_token.e0.valid || in_token.e0.index != core_index || in_token.e0.tag != core_tag); + = (!in_token.e2.valid || in_token.e2.index != core_index || in_token.e2.tag != core_tag) + && (!in_token.e1.valid || in_token.e1.index != core_index || in_token.e1.tag != core_tag) + && (!in_token.e0.valid || in_token.e0.index != core_index || in_token.e0.tag != core_tag); assign out_data = out_stall ? stall_data : out_data_next; assign out_data_next = send ? send_data : fwd_data; - assign out_data_valid = out_stall || send || (in_hold_valid && !last_hop); + assign out_data_valid = out_stall || send || (in_hold_valid && !last_hop && in_data_ready); assign send_data.tag = core_tag; assign send_data.ttl = `TTL_MAX; diff --git a/rtl/cache/routing.sv b/rtl/cache/routing.sv index 45e0296..c72d9b5 100644 --- a/rtl/cache/routing.sv +++ b/rtl/cache/routing.sv @@ -100,7 +100,7 @@ module cache_routing if (transition) begin mem_address <= cache_mem ? cache_mem_address : core_address_line; mem_writedata <= cache_mem ? cache_mem_writedata : core_writedata_line; - mem_byteenable <= cache_mem ? 16'hff : core_byteenable_line; + mem_byteenable <= cache_mem ? 16'hffff : core_byteenable_line; end endmodule diff --git a/tb/avalon.hpp b/tb/avalon.hpp index fd87c31..dc550f5 100644 --- a/tb/avalon.hpp +++ b/tb/avalon.hpp @@ -26,7 +26,9 @@ namespace taller::avalon std::uint32_t words[4]; }; - line() noexcept = default; + inline line() noexcept + : lo{0}, hi{0} + {} inline line(VlWide<4> verilated) noexcept : verilated(verilated) diff --git a/tb/sim/fibonacci.py b/tb/sim/fibonacci.py index f8bec8a..bf678a1 100644 --- a/tb/sim/fibonacci.py +++ b/tb/sim/fibonacci.py @@ -1,7 +1,7 @@ BASE = 0x0001_0000 COUNT = 20 -cycles = 1024 +cycles = 1024 + 512 mem_dumps = [range(BASE, BASE + 4 * COUNT)] def final(): |