diff options
Diffstat (limited to '')
| -rw-r--r-- | rtl/core/arm810.sv | 7 | ||||
| -rw-r--r-- | rtl/core/control/control.sv | 6 | ||||
| -rw-r--r-- | rtl/core/control/coproc.sv | 26 | ||||
| -rw-r--r-- | rtl/core/control/cycles.sv | 8 | ||||
| -rw-r--r-- | rtl/core/control/writeback.sv | 3 | ||||
| -rw-r--r-- | rtl/core/uarch.sv | 3 | ||||
| -rw-r--r-- | tb/sim/cpuid.S | 4 | ||||
| -rw-r--r-- | tb/sim/cpuid.py | 2 |
8 files changed, 45 insertions, 14 deletions
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 1771464..6b27b2b 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -173,14 +173,15 @@ module arm810 ); logic coproc; - word coproc_read, coproc_write; + word coproc_read; + coproc_decode coproc_ctrl; core_cp15 cp15 ( .transfer(coproc), - .dec(dec.coproc), + .dec(coproc_ctrl), .read(coproc_read), - .write(coproc_write), + .write(rd_value_a), .* ); diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 7658ee9..79d6d36 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -24,6 +24,7 @@ module core_control input logic mul_ready, input word mul_q_hi, mul_q_lo, + coproc_read, `ifdef VERILATOR input word insn, @@ -67,7 +68,8 @@ module core_control psr_write, psr_wr_flags, psr_wr_control, - output word psr_wr + output word psr_wr, + output coproc_decode coproc_ctrl ); ctrl_cycle cycle, next_cycle; @@ -152,6 +154,8 @@ module core_control .* ); + word coproc_wb; + core_control_coproc ctrl_cp ( .* diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv index 76f0a53..05ac655 100644 --- a/rtl/core/control/coproc.sv +++ b/rtl/core/control/coproc.sv @@ -2,21 +2,31 @@ module core_control_coproc ( - input logic clk, - rst_n, + input logic clk, + rst_n, - input insn_decode dec, + input insn_decode dec, + input word coproc_read, - input ctrl_cycle next_cycle, - input logic issue, + input ctrl_cycle next_cycle, + input logic issue, - output logic coproc + output logic coproc, + output word coproc_wb, + output coproc_decode coproc_ctrl ); always_ff @(posedge clk or negedge rst_n) - if(!rst_n) + if(!rst_n) begin coproc <= 0; - else if(next_cycle.issue && issue) + coproc_wb <= 0; + coproc_ctrl <= {$bits(coproc_ctrl){1'b0}}; + end else if(next_cycle.issue && issue) begin coproc <= dec.ctrl.coproc; + coproc_ctrl <= dec.coproc; + end else if(next_cycle.coproc) begin + coproc <= 0; + coproc_wb <= coproc_read; + end endmodule diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index 198c03b..88e0235 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -9,6 +9,7 @@ module core_control_cycles psr, ldst, bubble, + coproc, exception, mem_ready, mul_add, @@ -42,7 +43,8 @@ module core_control_cycles MUL, MUL_ACC_LD, MUL_HI_WB, - PSR + PSR, + COPROC } state, next_state; // TODO: debe estar escrito de tal forma que Quartus infiera una FSM @@ -58,6 +60,7 @@ module core_control_cycles assign cycle.mul_acc_ld = state == MUL_ACC_LD; assign cycle.mul_hi_wb = state == MUL_HI_WB; assign cycle.psr = state == PSR; + assign cycle.coproc = state == COPROC; assign next_cycle.issue = next_state == ISSUE; assign next_cycle.rd_indirect_shift = next_state == RD_INDIRECT_SHIFT; @@ -70,6 +73,7 @@ module core_control_cycles assign next_cycle.mul_acc_ld = next_state == MUL_ACC_LD; assign next_cycle.mul_hi_wb = next_state == MUL_HI_WB; assign next_cycle.psr = next_state == PSR; + assign next_cycle.coproc = next_state == COPROC; always_comb begin next_state = ISSUE; @@ -86,6 +90,8 @@ module core_control_cycles next_state = RD_INDIRECT_SHIFT; else if(!trivial_shift) next_state = WITH_SHIFT; + else if(coproc) + next_state = COPROC; RD_INDIRECT_SHIFT: if(!trivial_shift) diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 824d867..3bacb75 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -19,6 +19,7 @@ module core_control_writeback input word saved_base, vector, psr_wb, + coproc_wb, input reg_num ra, popped, mul_r_add_hi, @@ -68,6 +69,8 @@ module core_control_writeback wr_value = mul_q_lo; else if(cycle.psr) wr_value = psr_wb; + else if(cycle.coproc) + wr_value = coproc_wb; else // Ruta combinacional larga wr_value = q_alu; diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv index 74e536b..8ef0ae7 100644 --- a/rtl/core/uarch.sv +++ b/rtl/core/uarch.sv @@ -199,7 +199,8 @@ typedef struct packed mul, mul_acc_ld, mul_hi_wb, - psr; + psr, + coproc; } ctrl_cycle; typedef struct packed diff --git a/tb/sim/cpuid.S b/tb/sim/cpuid.S new file mode 100644 index 0000000..cde1786 --- /dev/null +++ b/tb/sim/cpuid.S @@ -0,0 +1,4 @@ +.global reset +reset: + mrc p15, 0, r0, c0, c0, 0 + mov pc, lr diff --git a/tb/sim/cpuid.py b/tb/sim/cpuid.py new file mode 100644 index 0000000..feb6b68 --- /dev/null +++ b/tb/sim/cpuid.py @@ -0,0 +1,2 @@ +def final(): + assert_reg(r0, 0x41018100); |