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-rw-r--r--conspiracion.qsf3
-rw-r--r--rtl/core/arm810.sv4
-rw-r--r--rtl/core/control/control.sv4
-rw-r--r--rtl/core/control/cycles.sv3
-rw-r--r--rtl/core/control/issue.sv3
-rw-r--r--rtl/core/control/stall.sv7
-rw-r--r--rtl/top/conspiracion.sv21
-rw-r--r--tb/top/conspiracion.cpp1
8 files changed, 35 insertions, 11 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf
index 76f962d..3d9db6a 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -109,6 +109,7 @@ set_global_assignment -name ECO_REGENERATE_REPORT ON
set_location_assignment PIN_AF14 -to clk_clk
set_location_assignment PIN_AB12 -to rst_n
+set_location_assignment PIN_AC12 -to halt
set_location_assignment PIN_V16 -to pio_leds[0]
set_location_assignment PIN_W16 -to pio_leds[1]
@@ -738,5 +739,5 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=516" -section_id auto_signaltap_0
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[26] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SLD_FILE db/bus_test_auto_stripped.stp
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 9b36a41..2600e51 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -5,13 +5,15 @@ module arm810
input logic clk,
rst_n,
irq,
+ halt,
output ptr bus_addr,
output logic bus_start,
bus_write,
input logic bus_ready,
input word bus_data_rd,
- output word bus_data_wr
+ output word bus_data_wr,
+ output logic halted
);
ptr fetch_insn_pc, fetch_head, insn_addr;
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 45e8e10..d204b96 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -4,6 +4,7 @@ module core_control
(
input logic clk,
rst_n,
+ halt,
input insn_decode dec,
input ptr insn_pc,
@@ -24,7 +25,8 @@ module core_control
input word insn,
`endif
- output logic stall,
+ output logic halted,
+ stall,
branch,
writeback,
update_flags,
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index 0a70d5e..0c5d94c 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -4,6 +4,7 @@ module core_control_cycles
(
input logic clk,
rst_n,
+ halt,
mul,
ldst,
bubble,
@@ -28,6 +29,8 @@ module core_control_cycles
ISSUE:
if(exception)
next_cycle = EXCEPTION;
+ else if(halt)
+ next_cycle = ISSUE;
else if(mul)
next_cycle = mul_add ? MUL_ACC_LD : MUL;
else if(data_snd_shift_by_reg)
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index e3eb338..b2ee6e5 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -4,6 +4,7 @@ module core_control_issue
(
input logic clk,
rst_n,
+ halt,
input insn_decode dec,
input ptr insn_pc,
@@ -22,7 +23,7 @@ module core_control_issue
next_pc_visible
);
- assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
+ assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble && !halt;
assign next_pc_visible = insn_pc + 2;
always_ff @(posedge clk or negedge rst_n)
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index 6d2b4e2..c2a6ddd 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -4,6 +4,7 @@ module core_control_stall
(
input logic clk,
rst_n,
+ halt,
input insn_decode dec,
@@ -14,7 +15,8 @@ module core_control_stall
writeback,
input reg_num final_rd,
- output logic stall,
+ output logic halted,
+ stall,
bubble,
next_bubble
);
@@ -22,7 +24,8 @@ module core_control_stall
logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard,
flags_hazard, flags_dependency, updating_flags;
- assign stall = next_cycle != ISSUE || next_bubble;
+ assign stall = next_cycle != ISSUE || next_bubble || halt;
+ assign halted = halt && !next_bubble;
assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard;
//FIXME: pc_rd_hazard no debería definirse sin final_writeback?
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index e6e1007..090271f 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -2,6 +2,7 @@ module conspiracion
(
input wire clk_clk,
input wire rst_n,
+ input wire halt,
output wire [12:0] memory_mem_a,
output wire [2:0] memory_mem_ba,
output wire memory_mem_ck,
@@ -41,27 +42,37 @@ module conspiracion
logic[29:0] addr;
logic[31:0] data_rd, data_wr;
- logic reset_reset_n, cpu_clk, cpu_rst_n, ready, write, start, irq;
-
-`ifndef VERILATOR`
- assign pio_leds[0] = reset_reset_n;
-`endif
+ logic reset_reset_n, cpu_clk, cpu_rst_n, cpu_halt, cpu_halted,
+ ready, write, start, irq;
`ifdef VERILATOR
+ assign cpu_halt = halt;
assign reset_reset_n = rst_n;
`else
+ assign pio_leds[0] = reset_reset_n;
+ assign pio_leds[1] = cpu_halted;
+
debounce reset_debounce
(
.clk(clk_clk),
.dirty(rst_n),
.clean(reset_reset_n)
);
+
+ debounce halt_debounce
+ (
+ .clk(cpu_clk),
+ .dirty(halt),
+ .clean(cpu_halt)
+ );
`endif
arm810 core
(
.clk(cpu_clk),
.rst_n(cpu_rst_n),
+ .halt(cpu_halt),
+ .halted(cpu_halted),
.bus_addr(addr),
.bus_data_rd(data_rd),
.bus_data_wr(data_wr),
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index 6af5d0b..ef9235d 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -230,6 +230,7 @@ int main(int argc, char **argv)
tick();
};
+ top.halt = 0;
top.rst_n = 0;
cycle();
top.rst_n = 1;