diff options
Diffstat (limited to '')
| -rw-r--r-- | conspiracion.qsf | 5 | ||||
| -rw-r--r-- | pitfalls.txt | 76 | ||||
| -rw-r--r-- | platform.qsys | 10 | ||||
| -rw-r--r-- | rtl/top/conspiracion.sv | 5 |
4 files changed, 88 insertions, 8 deletions
diff --git a/conspiracion.qsf b/conspiracion.qsf index acdf165..850a26a 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -192,8 +192,6 @@ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name ECO_REGENERATE_REPORT ON -set_location_assignment PIN_AF14 -to clk_clk - set_location_assignment PIN_AB12 -to dir set_location_assignment PIN_AA14 -to clr @@ -213,4 +211,7 @@ set_location_assignment PIN_Y21 -to done +set_location_assignment PIN_AF14 -to clk_clk + +set_global_assignment -name SDC_FILE conspiracion.sdc set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file diff --git a/pitfalls.txt b/pitfalls.txt index b77168e..67e2646 100644 --- a/pitfalls.txt +++ b/pitfalls.txt @@ -17,6 +17,7 @@ project again Nota: es *_pin_assignments.tcl y no ningún otro + === [II] Emulación de Avalon === @@ -28,3 +29,78 @@ lo segundo en una señal `s` hace que `assign a = s;` no tenga ningún efecto, lo cual es difícil de depurar. https://github.com/verilator/verilator/issues/2262 + + + === + [III] MSEL, uboot y fpga2sdram + === + +Solamente cambiar MSEL a 01010, convertir a rbf en Quartus y tratar de programar +desde uboot resulta en esto: + + SOCFPGA_CYCLONE5 # fpga load 0 ${fpgadata} ${fpgadatasize} + altera_load: Failed with error code -4 + +Hay que setear un modo en opciones de Quartus para que esto sirva. También puse +el MSEL en 00000 por si acaso. + +El manual dice que 00000 corresponde a FPPx16 + +https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/Altera-Cyclone-V-development-board-FPGA-problem-error-code-4/m-p/103855 + +Ahora pasa una de cuatro cosas con `mw 0xFFC2505C 0xA` (apply en registro staticcfg): + + 1. Hard-lock + 2. Data abort + 3. Prefetch abort + 4. Como 1/10 veces parece servir + +Sin apply la flag de done se queda levantada por siempre al tocar memoria. + +Hice de cero varias partes del Platform en Platform Designer, también desactivé +MPU events en hps_0 y cambié el data width de fpga2sdram de 64 a 256 bits. Todo +sigue igual. + +Si omito la instrucción que toca applycfg algo sirve. Escribir ya sirve +(confirmado con dd if=/dev/mem en HPS). Leer crashea el HPS tal como predice +zangman. + +Shintel al rescate: + +https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/embedded/2016/how-and-when-can-i-enable-the-fpga2sdram-bridge-on-cyclone-v-soc.html?utm_source=Altera&utm_medium=newsletter&utm_campaign=FACTS&utm_content=NA_how_can_i_enable_KI_15_08_2016 + +Bug exacto: +https://forum.rocketboards.org/t/fpga-to-sdram-cyclone-v-can-write-but-cannot-read/2796 + +Errata: +https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important_Note_about_FPGAHPS_SDRAM_Bridge + +El problema parece ser uno de dos: +- Me faltan las señales de burst +- uboot está en RAM cuando se toca applycfg + +Para lo segundo, errata dice que: + +Altera has provided the capability to set the configuration bit in step three +with a macro command in their (and Critical Link's) u-Boot port. This is +accomplished by copying a small routine to on-chip RAM that disables caches and +asserts the APPLYCFG bit and then returns operation to the typical DDR space. + +No sé donde putas está esa macro, así que voy a escribir mi propia:Ñ + +Info sobre OCRAM (on-chip RAM): https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html#sfo1410068453374.html#sfo1410068453374 + +sdram_staticcfg_applycfg: + dmb + dsb + isb + mov r0, #0x505c + movt r0, #0xffc2 + mov r1, #0xa + str r1, [r0] + dmb + dsb + mov r0, #0 + bx lr + +Esto solucionó todo diff --git a/platform.qsys b/platform.qsys index d9ab17c..f3f2bce 100644 --- a/platform.qsys +++ b/platform.qsys @@ -13,7 +13,7 @@ { datum _sortIndex { - value = "0"; + value = "1"; type = "int"; } } @@ -21,7 +21,7 @@ { datum _sortIndex { - value = "1"; + value = "2"; type = "int"; } } @@ -29,7 +29,7 @@ { datum _sortIndex { - value = "2"; + value = "0"; type = "int"; } } @@ -204,7 +204,7 @@ <parameter name="F2SCLK_SDRAMCLK_FREQ" value="0" /> <parameter name="F2SCLK_WARMRST_Enable" value="false" /> <parameter name="F2SDRAM_Type">Avalon-MM Bidirectional</parameter> - <parameter name="F2SDRAM_Width" value="64" /> + <parameter name="F2SDRAM_Width" value="256" /> <parameter name="F2SINTERRUPT_Enable" value="false" /> <parameter name="F2S_Width" value="0" /> <parameter name="FIX_READ_LATENCY" value="8" /> @@ -328,7 +328,7 @@ <parameter name="MEM_VERBOSE" value="true" /> <parameter name="MEM_VOLTAGE" value="1.5V DDR3" /> <parameter name="MEM_WTCL" value="6" /> - <parameter name="MPU_EVENTS_Enable" value="true" /> + <parameter name="MPU_EVENTS_Enable" value="false" /> <parameter name="MRS_MIRROR_PING_PONG_ATSO" value="false" /> <parameter name="MULTICAST_EN" value="false" /> <parameter name="NAND_Mode" value="N/A" /> diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv index 30aa95f..3177b98 100644 --- a/rtl/top/conspiracion.sv +++ b/rtl/top/conspiracion.sv @@ -17,13 +17,16 @@ module conspiracion output wire memory_mem_odt, output wire memory_mem_dm, input wire memory_oct_rzqin, - input wire reset_reset_n, + /*input wire reset_reset_n,*/ input logic dir, clr, mov, add, io, output logic[7:0] out, output logic done ); + wire reset_reset_n; + assign reset_reset_n = 1'b1; + enum { IDLE, IO, |