platform: implement support for disabling CPUs

2 files changed, 17 insertions, 39 deletions

diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index d8f5f62..e1f5f78 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -16,29 +16,7 @@
 #include <verilated_fst_c.h>
 #endif
 
-#include "Vtop.h"
-#include "Vtop_arm810.h"
-#include "Vtop_conspiracion.h"
-#include "Vtop_platform.h"
-#include "Vtop_sim_slave.h"
-#include "Vtop_vga_domain.h"
-#include "Vtop_core.h"
-#include "Vtop_core_control.h"
-#include "Vtop_core_control_issue.h"
-#include "Vtop_core_cp15_domain.h"
-#include "Vtop_core_cp15_far.h"
-#include "Vtop_core_cp15_fsr.h"
-#include "Vtop_core_cp15_syscfg.h"
-#include "Vtop_core_cp15_ttbr.h"
-#include "Vtop_core_cp15.h"
-#include "Vtop_core_fetch.h"
-#include "Vtop_core_mmu.h"
-#include "Vtop_core_psr.h"
-#include "Vtop_core_regs.h"
-#include "Vtop_core_reg_file.h"
-#include "Vtop_cache.h"
-#include "Vtop_cache__T1.h"
-#include "Vtop_cache_sram.h"
+#include "Vtop__Syms.h"
 
 #include "args.hxx"
 
@@ -414,17 +392,17 @@ int main(int argc, char **argv)
 	}
 
 	Vtop_arm810 *const cores[] = {
-		plat.cpu_0->cpu,
-		plat.cpu_1->cpu,
-		plat.cpu_2->cpu,
-		plat.cpu_3->cpu
+		plat.cpu_0->enable__DOT__cpu,
+		plat.cpu_1->enable__DOT__cpu,
+		plat.cpu_2->enable__DOT__cpu,
+		plat.cpu_3->enable__DOT__cpu
 	};
 
 	Vtop_cache_sram *const caches[] = {
-		plat.cache_0->sram,
-		plat.cache_1->sram,
-		plat.cache_2->sram,
-		plat.cache_3->sram
+		plat.cache_0->enable__DOT__sram,
+		plat.cache_1->enable__DOT__sram,
+		plat.cache_2->enable__DOT__sram,
+		plat.cache_3->enable__DOT__sram
 	};
 
 	for (const auto &init : init_regs) {
diff --git a/tb/top/conspiracion/platform.sv b/tb/top/conspiracion/platform.sv
index 054a302..9c6fb27 100644
--- a/tb/top/conspiracion/platform.sv
+++ b/tb/top/conspiracion/platform.sv
@@ -88,7 +88,7 @@ module platform
 	logic[1:0]  cpu_0_response, cpu_1_response, cpu_2_response, cpu_3_response;
 	logic[3:0]  cpu_0_byteenable, cpu_1_byteenable, cpu_2_byteenable, cpu_3_byteenable;
 
-	core cpu_0
+	core #(.ID(0)) cpu_0
 	(
 		.step(step_0),
 		.breakpoint(breakpoint_0),
@@ -106,7 +106,7 @@ module platform
 		.*
 	);
 
-	core cpu_1
+	core #(.ID(1)) cpu_1
 	(
 		.step(step_1),
 		.breakpoint(breakpoint_1),
@@ -125,7 +125,7 @@ module platform
 		.*
 	);
 
-	core cpu_2
+	core #(.ID(2)) cpu_2
 	(
 		.step(step_2),
 		.breakpoint(breakpoint_2),
@@ -144,7 +144,7 @@ module platform
 		.*
 	);
 
-	core cpu_3
+	core #(.ID(3)) cpu_3
 	(
 		.step(step_3),
 		.breakpoint(breakpoint_3),
@@ -177,7 +177,7 @@ module platform
 	      out_0_ready, out_1_ready, out_2_ready, out_3_ready,
 	      token_valid_0, token_valid_1, token_valid_2, token_valid_3;
 
-	cache cache_0
+	cache #(.ID(0)) cache_0
 	(
 		.core_address(cpu_0_address[31:2]),
 		.core_read(cpu_0_read),
@@ -233,7 +233,7 @@ module platform
 		.*
 	);
 
-	cache cache_1
+	cache #(.ID(1)) cache_1
 	(
 		.core_address(cpu_1_address[31:2]),
 		.core_read(cpu_1_read),
@@ -289,7 +289,7 @@ module platform
 		.*
 	);
 
-	cache cache_2
+	cache #(.ID(2)) cache_2
 	(
 		.core_address(cpu_2_address[31:2]),
 		.core_read(cpu_2_read),
@@ -345,7 +345,7 @@ module platform
 		.*
 	);
 
-	cache #(.TOKEN_AT_RESET(1)) cache_3
+	cache #(.ID(3)) cache_3
 	(
 		.core_address(cpu_3_address[31:2]),
 		.core_read(cpu_3_read),