diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-16 18:20:45 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-16 18:20:45 -0600 |
| commit | 87c73314d7ce0062b13ae14f376ec50a4653fb18 (patch) | |
| tree | d420e07e20066154442f3edde6c57606760ba81a /tb | |
| parent | a5468f968b46707e08eacf79847f1e12a4213ff7 (diff) | |
Implement register dumps
Diffstat (limited to '')
| -rw-r--r-- | tb/sim/hazards.py | 3 | ||||
| -rwxr-xr-x | tb/sim/sim.py | 14 | ||||
| -rw-r--r-- | tb/top/conspiracion.cpp | 70 |
3 files changed, 74 insertions, 13 deletions
diff --git a/tb/sim/hazards.py b/tb/sim/hazards.py index 9fa3e44..b89b15b 100644 --- a/tb/sim/hazards.py +++ b/tb/sim/hazards.py @@ -1,9 +1,10 @@ SP = 256 +cycles = 256 mem_dumps = [range(SP - 4, SP)] def final(): assert_reg(r0, 59) assert_reg(r1, 0) - assert_reg(sp, SP) + assert_reg(sp_svc, SP) assert_mem(SP - 4, 3) diff --git a/tb/sim/sim.py b/tb/sim/sim.py index 9a239e9..dd0f72e 100755 --- a/tb/sim/sim.py +++ b/tb/sim/sim.py @@ -33,6 +33,12 @@ all_regs = { 'r12_usr': 'r12_usr', 'r12_fiq': 'r12_fiq', 'sp': 'r13_usr', + 'sp_usr': 'r13_usr', + 'sp_svc': 'r13_svc', + 'sp_abt': 'r13_abt', + 'sp_und': 'r13_und', + 'sp_irq': 'r13_irq', + 'sp_fiq': 'r13_fiq', 'r13': 'r13_usr', 'r13_usr': 'r13_usr', 'r13_svc': 'r13_svc', @@ -41,6 +47,12 @@ all_regs = { 'r13_irq': 'r13_irq', 'r13_fiq': 'r13_fiq', 'lr': 'r14_usr', + 'lr_usr': 'r14_usr', + 'lr_svc': 'r14_svc', + 'lr_abt': 'r14_abt', + 'lr_und': 'r14_und', + 'lr_irq': 'r14_irq', + 'lr_fiq': 'r14_fiq', 'r14': 'r14_usr', 'r14_usr': 'r14_usr', 'r14_svc': 'r14_svc', @@ -166,4 +178,4 @@ for line in output.stdout.split('\n'): if final := module_get('final'): final() -print(f'Test \'{test_name}\' passed', file=sys.stderr) +print(f'\033[32mTest \'\033[33;1m{test_name}\033[0m\033[32m\' passed\033[0m', file=sys.stderr) diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp index 77047e7..2408ecc 100644 --- a/tb/top/conspiracion.cpp +++ b/tb/top/conspiracion.cpp @@ -8,27 +8,67 @@ #include <verilated_vcd_c.h> #include "Vconspiracion.h" +#include "Vconspiracion_arm810.h" #include "Vconspiracion_conspiracion.h" #include "Vconspiracion_platform.h" +#include "Vconspiracion_core_regs.h" +#include "Vconspiracion_core_reg_file.h" #include "../args.hxx" #include "../avalon.hpp" #include "../mem.hpp" -struct mem_region +namespace { - std::size_t start; - std::size_t length; -}; + struct mem_region + { + std::size_t start; + std::size_t length; + }; -std::istream &operator>>(std::istream &stream, mem_region ®ion) -{ - stream >> region.start; - stream.get(); - stream >> region.length; - return stream; + std::istream &operator>>(std::istream &stream, mem_region ®ion) + { + stream >> region.start; + stream.get(); + stream >> region.length; + return stream; + } + + constexpr const char *gp_regs[30] = + { + [0] = "0", + [1] = "1", + [2] = "2", + [3] = "3", + [4] = "4", + [5] = "5", + [6] = "6", + [7] = "7", + [8] = "8_usr", + [9] = "9_usr", + [10] = "10_usr", + [11] = "11_usr", + [12] = "12_usr", + [13] = "13_usr", + [14] = "14_usr", + [15] = "8_fiq", + [16] = "9_fiq", + [17] = "10_fiq", + [18] = "11_fiq", + [19] = "12_fiq", + [20] = "13_fiq", + [21] = "14_fiq", + [22] = "13_irq", + [23] = "14_irq", + [24] = "13_und", + [25] = "14_und", + [26] = "13_abt", + [27] = "14_abt", + [28] = "13_svc", + [29] = "14_svc", + }; } int main(int argc, char **argv) @@ -142,6 +182,14 @@ int main(int argc, char **argv) if(dump_regs) { std::puts("=== dump-regs ==="); + + const auto ®file = top.conspiracion->core->regs->a->file; + + int i = 0; + for(const auto *name : gp_regs) + { + std::printf("%08x r%s\n", regfile[i++], name); + } } const auto &dumps = *dump_mem; @@ -152,7 +200,7 @@ int main(int argc, char **argv) for(const auto &dump : dumps) { - std::printf("%08x ", dump.start); + std::printf("%08x ", static_cast<std::uint32_t>(dump.start)); for(std::size_t i = 0; i < dump.length; ++i) { auto word = avl.dump(dump.start + i); |
