diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-16 16:46:52 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-16 17:55:27 -0600 |
| commit | 683352ce030923bdef3cf4fe90d6cb73f4f74529 (patch) | |
| tree | 09bfdff34626fe90a10d93df2c293f7d87763e44 /tb | |
| parent | 14a3611e492d2f213e81c9053bf613a5d8ad30a6 (diff) | |
Implement psr read/write logic
Diffstat (limited to '')
| -rw-r--r-- | tb/sim/modeswitch.S | 3 | ||||
| -rw-r--r-- | tb/sim/modeswitch.py | 11 |
2 files changed, 11 insertions, 3 deletions
diff --git a/tb/sim/modeswitch.S b/tb/sim/modeswitch.S index c04f8a3..52908de 100644 --- a/tb/sim/modeswitch.S +++ b/tb/sim/modeswitch.S @@ -1,5 +1,6 @@ .global reset reset: + mov r6, lr mrs r0, cpsr udf mrs r2, cpsr @@ -12,7 +13,7 @@ reset: nop msr cpsr_fxc, r0 msr spsr_fxc, r0 - mov pc, lr + mov pc, r6 .global undefined undefined: diff --git a/tb/sim/modeswitch.py b/tb/sim/modeswitch.py index 6919f2e..6c8cd79 100644 --- a/tb/sim/modeswitch.py +++ b/tb/sim/modeswitch.py @@ -1,3 +1,10 @@ def final(): - #TODO - assert_reg(r0, -1) + assert_reg(r0, 0x0000_01d3) + assert_reg(r1, 0x0000_01d3) + assert_reg(r2, 0x0000_01d3) + assert_reg(r3, 0x0000_0010) + assert_reg(r4, 0x0000_0110) + assert_reg(r5, 0x4000_0110) + assert_reg(cpsr, 0x0000_0110) + assert_reg(r13_svc, 0x2000_0000) + assert_reg(r13_und, 0x0000_01db) |