diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-11-15 19:10:34 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-11-16 16:43:59 -0600 |
| commit | 87a42e555bf952047e287f4c7810cd538595d5af (patch) | |
| tree | d08db58fc3484bae6d63e5b2d69e66bf8c11cf95 /tb/top | |
| parent | ba803067cb54edece9ffa8b92f9bb97317d082e5 (diff) | |
rtl/smp: implement SMP dead/alive handling
Diffstat (limited to 'tb/top')
| -rw-r--r-- | tb/top/conspiracion/platform.sv | 5 | ||||
| -rw-r--r-- | tb/top/test_smp.py | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/tb/top/conspiracion/platform.sv b/tb/top/conspiracion/platform.sv index 9c6fb27..6302d53 100644 --- a/tb/top/conspiracion/platform.sv +++ b/tb/top/conspiracion/platform.sv @@ -93,6 +93,7 @@ module platform .step(step_0), .breakpoint(breakpoint_0), .cpu_halt(halt_0), + .cpu_alive(cpu_alive_0), .cpu_halted(cpu_halted_0), .avl_address(cpu_0_address), .avl_read(cpu_0_read), @@ -111,6 +112,7 @@ module platform .step(step_1), .breakpoint(breakpoint_1), .cpu_halt(halt_1), + .cpu_alive(cpu_alive_1), .cpu_halted(cpu_halted_1), .avl_address(cpu_1_address), .avl_read(cpu_1_read), @@ -130,6 +132,7 @@ module platform .step(step_2), .breakpoint(breakpoint_2), .cpu_halt(halt_2), + .cpu_alive(cpu_alive_2), .cpu_halted(cpu_halted_2), .avl_address(cpu_2_address), .avl_read(cpu_2_read), @@ -149,6 +152,7 @@ module platform .step(step_3), .breakpoint(breakpoint_3), .cpu_halt(halt_3), + .cpu_alive(cpu_alive_3), .cpu_halted(cpu_halted_3), .avl_address(cpu_3_address), .avl_read(cpu_3_read), @@ -419,6 +423,7 @@ module platform logic step_0, step_1, step_2, step_3, halt_0, halt_1, halt_2, halt_3, breakpoint_0, breakpoint_1, breakpoint_2, breakpoint_3, + cpu_alive_0, cpu_alive_1, cpu_alive_2, cpu_alive_3, cpu_halted_0, cpu_halted_1, cpu_halted_2, cpu_halted_3; smp_ctrl smp diff --git a/tb/top/test_smp.py b/tb/top/test_smp.py index a3cb61f..b7903ce 100644 --- a/tb/top/test_smp.py +++ b/tb/top/test_smp.py @@ -9,6 +9,11 @@ from tb.models import CorePaceModel, SmpModel async def bring_up(dut): await cocotb.start(Clock(dut.clk, 2).start()) + dut.cpu_alive_0.value = 1 + dut.cpu_alive_1.value = 1 + dut.cpu_alive_2.value = 1 + dut.cpu_alive_3.value = 1 + dut.rst_n.value = 1 await Timer(1) dut.rst_n.value = 0 |