diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-25 08:46:56 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-25 08:52:29 -0600 |
| commit | 746da8fe47003997ae0b762fe325c7fa8040cafb (patch) | |
| tree | 78f743b46cf02cb303a06540e532ece3d1f868f3 /tb/sim | |
| parent | 2864ed33089d43a898928095de01eefecaf448e4 (diff) | |
Add sim test: tarea2
Diffstat (limited to 'tb/sim')
| -rw-r--r-- | tb/sim/tarea2.S | 44 | ||||
| -rw-r--r-- | tb/sim/tarea2.py | 23 |
2 files changed, 67 insertions, 0 deletions
diff --git a/tb/sim/tarea2.S b/tb/sim/tarea2.S new file mode 100644 index 0000000..c372672 --- /dev/null +++ b/tb/sim/tarea2.S @@ -0,0 +1,44 @@ +@ Tarea 2, CE3201 Taller de Diseño Digital +@ Alejandro Soto Chacón, 2019008164 + +.global fibonacci +fibonacci: + mov r0, #0x150 + ldr r0, [r0] + mov r1, #0x200 + mov r2, #1 + mov r3, #1 + mov r4, #0 + tst r0, r0 + beq .end + ldr r6, =10000 @ Relativo a PC + .loop: + add r5, r2, r3 + add r4, r4, r2 + str r2, [r1], #4 + mov r2, r3 + mov r3, r5 + cmp r4, r6 + bhi .end + subs r0, r0, #1 + bne .loop + .end: + mov r5, #0x100 + str r4, [r5], #4 + mov r4, #0xff + mov r6, #0xaa + @ Necesariamente se cumple alguna de las dos condiciones + @ ya que una es la opuesta de la otra + strhi r4, [r5] + strls r6, [r5] + mov pc, lr + +@ Punto de entrada, requerido ya que el simulador solamente es capaz +@ ed establecer condiciones iniciales de registros, no de memoria. +@ En este caso se pasa el número de iteraciones en r0 y el stub lo +@ escribe en la posición correcta. +.global reset +reset: + mov r1, #0x150 + str r0, [r1] + b fibonacci diff --git a/tb/sim/tarea2.py b/tb/sim/tarea2.py new file mode 100644 index 0000000..921ea6f --- /dev/null +++ b/tb/sim/tarea2.py @@ -0,0 +1,23 @@ +N = 20 + +mem_dumps = [range(0x100, 0x108), range(0x200, 0x200 + 4 * N)] + +def init(): + init_reg(r0, N) + +def final(): + a, b, s = 1, 1, 0 + mem = [] + + for _ in range(N): + s += a + c = a + b + mem.append(a) + a, b = b, c + + if s > 10000: + break + + assert_reg(r5, 0x104) + assert_mem(0x100, [s, 0xff if s > 10000 else 0xaa]) + assert_mem(0x200, mem) |
