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authorAlejandro Soto <alejandro@34project.org>2022-12-09 01:43:23 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-09 01:43:23 -0600
commit02f76bae32e295bf1da04e38dfa12dfbc5832aec (patch)
tree4fd1d1c68a7a81a5b479437537e29ae5121a33b2 /tb/sim
parentb2b2d5124db13714ed82181c9558568d908dfa2a (diff)
Implement CP15 ID register
Diffstat (limited to 'tb/sim')
-rw-r--r--tb/sim/cpuid.S6
-rw-r--r--tb/sim/cpuid.py6
2 files changed, 10 insertions, 2 deletions
diff --git a/tb/sim/cpuid.S b/tb/sim/cpuid.S
index cde1786..5c0ddf8 100644
--- a/tb/sim/cpuid.S
+++ b/tb/sim/cpuid.S
@@ -1,4 +1,8 @@
.global reset
reset:
- mrc p15, 0, r0, c0, c0, 0
+ mrc p15, 0, r0, c0, c0, 0b000
+ mrc p15, 0, r1, c0, c0, 0b001
+ mrc p15, 0, r2, c0, c0, 0b010
+ mrc p15, 0, r3, c0, c0, 0b011
+ mrc p15, 0, r4, c0, c0, 0b100
mov pc, lr
diff --git a/tb/sim/cpuid.py b/tb/sim/cpuid.py
index feb6b68..15c9529 100644
--- a/tb/sim/cpuid.py
+++ b/tb/sim/cpuid.py
@@ -1,2 +1,6 @@
def final():
- assert_reg(r0, 0x41018100);
+ assert_reg(r0, 0x41018100)
+ assert_reg(r1, 0x0310a10a)
+ assert_reg(r2, 0x00000000)
+ assert_reg(r3, 0x00000001)
+ assert_reg(r4, 0x00000000)