diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-11 14:48:08 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-16 16:27:20 -0600 |
| commit | ff71bcd0c5425c168f111b8f4a92d0a90a6c9c31 (patch) | |
| tree | 41190239b9220db09d8849afb6d6f6dbbc03f59b /tb/sim | |
| parent | 6fee344b754464b1fd17f7c0429e6597e51dc74d (diff) | |
Implement data aborts
Diffstat (limited to 'tb/sim')
| -rw-r--r-- | tb/sim/paging.S | 57 | ||||
| -rw-r--r-- | tb/sim/paging.py | 3 |
2 files changed, 37 insertions, 23 deletions
diff --git a/tb/sim/paging.S b/tb/sim/paging.S index a2c1d14..b1dee0e 100644 --- a/tb/sim/paging.S +++ b/tb/sim/paging.S @@ -1,7 +1,13 @@ +.global data_abort +data_abort: + mrc p15, 0, r2, c6, c0, 0 + mrc p15, 0, r3, c5, c0, 0 + mov pc, r4 + .global reset reset: # Copy code to page 3 - ldr r0, =virtual_start + ldr r0, =.virtual_start ldr r1, =0x3000 ldr r2, =256 .copy_virtual: @@ -11,32 +17,37 @@ reset: bne .copy_virtual # Translation tables - mov r0, #0x4000 - ldr r1, =0x00005001 - str r1, [r0] + mov r0, #0x4000 + ldr r1, =0x00005001 + str r1, [r0] - mov r1, #0x5000 - ldr r2, =0x00000002 - str r2, [r1], #4 - str r2, [r1], #4 - str r2, [r1], #4 - str r2, [r1], #4 - ldr r2, =0x00003002 - str r2, [r1], #4 + mov r1, #0x5000 + ldr r2, =0x00000002 + str r2, [r1], #4 + str r2, [r1], #4 + str r2, [r1], #4 + str r2, [r1], #4 + ldr r2, =0x00003002 + str r2, [r1], #4 # Set translation base and enable MMU - mov r1, #(1 << 0) - mcr p15, 0, r0, c2, c0, 0 - mcr p15, 0, r1, c1, c0, 0 + mov r1, #(1 << 0) + mcr p15, 0, r0, c2, c0, 0 + mcr p15, 0, r1, c1, c0, 0 # Self-relocate to 0x2000 (mirror of 0x0000) - ldr r1, =#(0x2000 - 4) - add pc, pc, r1 + ldr r1, =#(0x2000 - 4) + add pc, pc, r1 - # Jump to virtual_start (phys: 0x3000, virt: 0x4000) - ldr r0, =0x01234567 - ldr pc, =0x4000 + # Jump to .virtual_start (phys: 0x3000, virt: 0x4000) + ldr r0, =0x01234567 + ldr pc, =0x4000 + b . -virtual_start: - ldr r1, =0x89abcdef - mov pc, lr + .virtual_start: + ldr r1, =0x89abcdef + and r6, r1, #~0xf + mov r4, lr + mov r5, lr + # This triggers a page fault + ldr r4, [r6] diff --git a/tb/sim/paging.py b/tb/sim/paging.py index 799f03d..2249be0 100644 --- a/tb/sim/paging.py +++ b/tb/sim/paging.py @@ -3,3 +3,6 @@ cycles = 4096 def final(): assert_reg(r0, 0x01234567) assert_reg(r1, 0x89abcdef) + assert_reg(r2, 0x89abcde0) + assert_reg(r3, 0) + assert_reg(r4, read_reg(r5)) |