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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-19 21:19:18 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-19 21:19:18 -0600 |
| commit | 6ebe514137fa41ac015122da4dcaba56af84e531 (patch) | |
| tree | 0582d0684f130b08ec2b7ea73d57642485245ccf /tb/sim/sim.py | |
| parent | 8ec66f50c64501e30ed6adae94f89b90b48de7f0 (diff) | |
Implement JTAG-UART input
Diffstat (limited to 'tb/sim/sim.py')
| -rwxr-xr-x | tb/sim/sim.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tb/sim/sim.py b/tb/sim/sim.py index b14e0fd..91fc348 100755 --- a/tb/sim/sim.py +++ b/tb/sim/sim.py @@ -249,7 +249,7 @@ mem_dumps = module_get('mem_dumps', []) if init := module_get('init'): init() -exec_args = [verilated, '--headless', '--cycles', str(cycles), '--dump-regs'] +exec_args = [verilated, '--headless', '--no-tty', '--cycles', str(cycles), '--dump-regs'] for rng in mem_dumps: length = rng.stop - rng.start |