diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-16 18:20:45 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-16 18:20:45 -0600 |
| commit | 87c73314d7ce0062b13ae14f376ec50a4653fb18 (patch) | |
| tree | d420e07e20066154442f3edde6c57606760ba81a /tb/sim/sim.py | |
| parent | a5468f968b46707e08eacf79847f1e12a4213ff7 (diff) | |
Implement register dumps
Diffstat (limited to 'tb/sim/sim.py')
| -rwxr-xr-x | tb/sim/sim.py | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/tb/sim/sim.py b/tb/sim/sim.py index 9a239e9..dd0f72e 100755 --- a/tb/sim/sim.py +++ b/tb/sim/sim.py @@ -33,6 +33,12 @@ all_regs = { 'r12_usr': 'r12_usr', 'r12_fiq': 'r12_fiq', 'sp': 'r13_usr', + 'sp_usr': 'r13_usr', + 'sp_svc': 'r13_svc', + 'sp_abt': 'r13_abt', + 'sp_und': 'r13_und', + 'sp_irq': 'r13_irq', + 'sp_fiq': 'r13_fiq', 'r13': 'r13_usr', 'r13_usr': 'r13_usr', 'r13_svc': 'r13_svc', @@ -41,6 +47,12 @@ all_regs = { 'r13_irq': 'r13_irq', 'r13_fiq': 'r13_fiq', 'lr': 'r14_usr', + 'lr_usr': 'r14_usr', + 'lr_svc': 'r14_svc', + 'lr_abt': 'r14_abt', + 'lr_und': 'r14_und', + 'lr_irq': 'r14_irq', + 'lr_fiq': 'r14_fiq', 'r14': 'r14_usr', 'r14_usr': 'r14_usr', 'r14_svc': 'r14_svc', @@ -166,4 +178,4 @@ for line in output.stdout.split('\n'): if final := module_get('final'): final() -print(f'Test \'{test_name}\' passed', file=sys.stderr) +print(f'\033[32mTest \'\033[33;1m{test_name}\033[0m\033[32m\' passed\033[0m', file=sys.stderr) |
