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authorAlejandro Soto <alejandro@34project.org>2022-11-08 21:33:59 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-08 21:33:59 -0600
commit1ea0519a2b6b81e0ba324cd69f8785735e7cbef5 (patch)
treea89c1aa54fac62b1b849aa147c4c7ee1b42d4601 /tb/sim/sdram.py
parentbf7f350e161b2dc97e023724c8f190473af78202 (diff)
Fix handling of multi-cycle Avalon waitrequest states in bus master
Diffstat (limited to '')
-rw-r--r--tb/sim/sdram.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tb/sim/sdram.py b/tb/sim/sdram.py
index 2225941..fbc2c97 100644
--- a/tb/sim/sdram.py
+++ b/tb/sim/sdram.py
@@ -1,7 +1,7 @@
START = 0x0000_1000
END = 0x0000_2000
-cycles = 15000
+cycles = 30000
mem_dumps = [range(START, END)]
def final():