summaryrefslogtreecommitdiff
path: root/tb/sim/fibonacci.py
diff options
context:
space:
mode:
authorAlejandro Soto <alejandro@34project.org>2022-11-08 21:33:59 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-08 21:33:59 -0600
commit1ea0519a2b6b81e0ba324cd69f8785735e7cbef5 (patch)
treea89c1aa54fac62b1b849aa147c4c7ee1b42d4601 /tb/sim/fibonacci.py
parentbf7f350e161b2dc97e023724c8f190473af78202 (diff)
Fix handling of multi-cycle Avalon waitrequest states in bus master
Diffstat (limited to '')
-rw-r--r--tb/sim/fibonacci.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/tb/sim/fibonacci.py b/tb/sim/fibonacci.py
index fb20b63..f8bec8a 100644
--- a/tb/sim/fibonacci.py
+++ b/tb/sim/fibonacci.py
@@ -1,7 +1,7 @@
BASE = 0x0001_0000
COUNT = 20
-cycles = 500
+cycles = 1024
mem_dumps = [range(BASE, BASE + 4 * COUNT)]
def final():