diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-15 23:18:09 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-15 23:31:30 -0600 |
| commit | d9dfa098323bc9ffdc9e976bd4106efc75b2954a (patch) | |
| tree | 60753d507eb5a936eb80ae30c0b239b7480c5e8e /tb/platform.sv | |
| parent | 8ab171864291c74d0a22cac911bc8a8aee8a7d5b (diff) | |
Implemente byte-enable signal in stores
Diffstat (limited to 'tb/platform.sv')
| -rw-r--r-- | tb/platform.sv | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/tb/platform.sv b/tb/platform.sv index 5fcb9f2..1e708cc 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -1,12 +1,13 @@ module platform ( input wire clk_clk, // clk.clk - input wire [29:0] master_0_core_addr /*verilator public*/,// master_0_core.addr - output wire [31:0] master_0_core_data_rd /*verilator public*/,// .data_rd - input wire [31:0] master_0_core_data_wr /*verilator public*/,// .data_wr - output wire master_0_core_ready /*verilator public*/,// .ready - input wire master_0_core_write /*verilator public*/,// .write - input wire master_0_core_start /*verilator public*/,// .start + input wire [29:0] master_0_core_addr, // master_0_core.addr + output wire [31:0] master_0_core_data_rd, // .data_rd + input wire [31:0] master_0_core_data_wr, // .data_wr + input wire [3:0] master_0_core_data_be, // .data_be + output wire master_0_core_ready, // .ready + input wire master_0_core_write, // .write + input wire master_0_core_start, // .start output wire master_0_core_irq, // .irq output wire master_0_core_cpu_clk, // .cpu_clk output wire master_0_core_cpu_rst_n, @@ -68,6 +69,7 @@ module platform .ready(master_0_core_ready), .data_rd(master_0_core_data_rd), .data_wr(master_0_core_data_wr), + .data_be(master_0_core_data_be), .cpu_clk(master_0_core_cpu_clk), .cpu_rst_n(master_0_core_cpu_rst_n), .irq(master_0_core_irq), |