diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-12 21:25:37 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:54:44 -0600 |
| commit | 9a1dd87d89d3cb57fe0d811e462b9348234eae79 (patch) | |
| tree | f93aa77748527ecedcc18bae629b8d81a7eb0a4d /tb/platform.sv | |
| parent | 7d171c1e3ae6dab855ee264e7926281c3a4d25ca (diff) | |
Route cpu_rst_n signal through bus master
Diffstat (limited to 'tb/platform.sv')
| -rw-r--r-- | tb/platform.sv | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tb/platform.sv b/tb/platform.sv index 21fb45b..cbf31b0 100644 --- a/tb/platform.sv +++ b/tb/platform.sv @@ -12,6 +12,7 @@ module platform input wire master_0_core_start /*verilator public*/,// .start output wire master_0_core_irq, // .irq output wire master_0_core_cpu_clk, // .cpu_clk + output wire master_0_core_cpu_rst_n, output wire [12:0] memory_mem_a, // memory.mem_a output wire [2:0] memory_mem_ba, // .mem_ba output wire memory_mem_ck, // .mem_ck @@ -71,6 +72,7 @@ module platform .data_rd(master_0_core_data_rd), .data_wr(master_0_core_data_wr), .cpu_clk(master_0_core_cpu_clk), + .cpu_rst_n(master_0_core_cpu_rst_n), .irq(master_0_core_irq), .* ); |