tb: implement support for cache line-sized slaves

1 files changed, 22 insertions, 7 deletions

diff --git a/tb/mem.hpp b/tb/mem.hpp
index 0943530..4c37b0e 100644
--- a/tb/mem.hpp
+++ b/tb/mem.hpp
@@ -8,30 +8,45 @@
 
 namespace taller::avalon
 {
-	template<typename Cell>
 	class mem : public slave
 	{
 		public:
 			mem(std::uint32_t base, std::uint32_t size);
 
-			virtual bool read(std::uint32_t addr, std::uint32_t &data) final override;
+			virtual bool read_line(std::uint32_t addr, line &data) final override;
 
-			virtual bool write
+			virtual bool write_line
 			(
-				std::uint32_t addr, std::uint32_t data, unsigned byte_enable = 0b1111
+				std::uint32_t addr, const line &data, unsigned byte_enable
 			) final override;
 
 			template<typename F>
 			void load(F loader, std::size_t offset = 0);
 
 		private:
-			std::unique_ptr<Cell[]> block;
+			std::unique_ptr<line[]> block;
 			unsigned                count = 0;
 
 			bool ready() noexcept;
 	};
-}
 
-#include "mem.impl.hpp"
+	template<typename F>
+	void mem::load(F loader, std::size_t offset)
+	{
+		const auto base = base_address();
+		const auto bits = 4;
+
+		std::size_t size = address_span();
+		std::size_t addr = base_address() + offset;
+
+		while (addr >= base && addr < base + size) {
+			std::size_t read = loader(&block[(addr - base) >> bits], (base + size - addr) >> bits);
+			if (!read)
+				break;
+
+			addr += read << bits;
+		}
+	}
+}
 
 #endif