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authorAlejandro Soto <alejandro@34project.org>2022-12-12 11:47:02 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:29:10 -0600
commitc67d424c6d130f810c251576fd55389d1385edb5 (patch)
treeb274f3f80d0d06457696a53b35bb98bbfe572035 /sim
parent79e05aa7f0ccce6eb26248ddef3e928727857a9c (diff)
Show main cp15 registers in register dumps
Diffstat (limited to 'sim')
-rwxr-xr-xsim/sim.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/sim/sim.py b/sim/sim.py
index 448c39f..6ef0ed0 100755
--- a/sim/sim.py
+++ b/sim/sim.py
@@ -68,6 +68,10 @@ all_regs = [
('spsr_und', 'spsr_und'),
('spsr_irq', 'spsr_irq'),
('spsr_fiq', 'spsr_fiq'),
+ ('sysctrl', 'sysctrl'),
+ ('ttbr', 'ttbr'),
+ ('far', 'far'),
+ ('fsr', 'fsr'),
]
regs = {}