Fix implementation of MMU access faults

1 files changed, 1 insertions, 0 deletions

diff --git a/sim/sim.py b/sim/sim.py
index 4a1dfa8..03d45c7 100755
--- a/sim/sim.py
+++ b/sim/sim.py
@@ -72,6 +72,7 @@ all_regs = [
     ('ttbr', 'ttbr'),
     ('far', 'far'),
     ('fsr', 'fsr'),
+    ('dacr', 'dacr'),
     ]
 
 regs = {}