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| author | Alejandro Soto <alejandro@34project.org> | 2022-12-07 20:04:15 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-07 20:04:23 -0600 |
| commit | a7adc0af074826a4c68c7395d2abfd4b931955df (patch) | |
| tree | e9db6027bf690ad17e66a97334a52e7f8790d36f /sim/sim.py | |
| parent | c39552375661e495b344e8386649ade92a4d45b2 (diff) | |
Make the cycle limit optional
Diffstat (limited to 'sim/sim.py')
| -rwxr-xr-x | sim/sim.py | 7 |
1 files changed, 5 insertions, 2 deletions
@@ -275,13 +275,16 @@ prelude.update({k: v for k, v in all_regs}) module.__dict__.update(prelude) spec.loader.exec_module(module) -cycles = module_get('cycles', 1024) mem_dumps = module_get('mem_dumps', []) if init := module_get('init'): init() -exec_args = [verilated, '--headless', '--no-tty', '--cycles', str(cycles), '--dump-regs'] +exec_args = [verilated, '--headless', '--no-tty', '--dump-regs'] + +cycles = module_get('cycles', 1024) +if cycles is not None: + exec_args.extend(['--cycles', str(cycles)]) for rng in mem_dumps: length = rng.stop - rng.start |
