ip: add ip_fp_inv

4 files changed, 39 insertions, 2 deletions

diff --git a/rtl/gfx/fp_add.sv b/rtl/gfx/fp_add.sv
index e8e0c5f..b49a8aa 100644
--- a/rtl/gfx/fp_add.sv
+++ b/rtl/gfx/fp_add.sv
@@ -23,7 +23,7 @@ module fp_add
 
 	integer i;
 
-	always @(posedge clk)
+	always_ff @(posedge clk)
 		if (!stall) begin
 			a_pipeline[0] <= a;
 			b_pipeline[0] <= b;
diff --git a/rtl/gfx/fp_inv.sv b/rtl/gfx/fp_inv.sv
new file mode 100644
index 0000000..d2bebdc
--- /dev/null
+++ b/rtl/gfx/fp_inv.sv
@@ -0,0 +1,36 @@
+`include "gfx/gfx_defs.sv"
+
+module fp_inv
+(
+	input  logic clk,
+
+	input  fp    a,
+	input  logic stall,
+
+	output fp    q
+);
+
+`ifndef VERILATOR
+	ip_fp_inv ip_inv
+	(
+		.en(!stall),
+		.areset(0),
+		.*
+	);
+`else
+	fp pipeline[`FP_INV_STAGES - 1];
+
+	integer i;
+
+	always_ff @(posedge clk)
+		if (!stall) begin
+			pipeline[0] <= a;
+
+			for (i = 1; i < `FP_INV_STAGES - 1; ++i)
+				pipeline[i] <= pipeline[i - 1];
+
+			q <= $c("taller::fp_inv(", pipeline[`FP_INV_STAGES - 2], ")");
+		end
+`endif
+
+endmodule
diff --git a/rtl/gfx/fp_mul.sv b/rtl/gfx/fp_mul.sv
index af5e09c..fda4de2 100644
--- a/rtl/gfx/fp_mul.sv
+++ b/rtl/gfx/fp_mul.sv
@@ -23,7 +23,7 @@ module fp_mul
 
 	integer i;
 
-	always @(posedge clk)
+	always_ff @(posedge clk)
 		if (!stall) begin
 			a_pipeline[0] <= a;
 			b_pipeline[0] <= b;
diff --git a/rtl/gfx/gfx_defs.sv b/rtl/gfx/gfx_defs.sv
index 01b7116..1fe0df2 100644
--- a/rtl/gfx/gfx_defs.sv
+++ b/rtl/gfx/gfx_defs.sv
@@ -9,6 +9,7 @@
 // Target de 200MHz (reloj es 143MHz) con float16, rounding aproximado
 `define FP_ADD_STAGES 10 // ~401 LUTs
 `define FP_MUL_STAGES 5  // ~144 LUTs ~1 bloque DSP
+`define FP_INV_STAGES 3  // ~178 LUTs ~1 bloque DSP
 
 typedef logic[`FLOAT_BITS - 1:0] fp;
 typedef fp                       vec2[2];