Expose cp15 signals to core toplevel

6 files changed, 20 insertions, 15 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 6b27b2b..1fd408f 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -1,3 +1,4 @@
+`include "core/mmu/format.sv"
 `include "core/uarch.sv"
 
 module arm810
@@ -172,8 +173,9 @@ module arm810
 		.*
 	);
 
-	logic coproc;
 	word coproc_read;
+	logic coproc, high_vectors, mmu_enable;
+	mmu_base mmu_ttbr;
 	coproc_decode coproc_ctrl;
 
 	core_cp15 cp15
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 79d6d36..3c55507 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -25,6 +25,7 @@ module core_control
 	input  word            mul_q_hi,
 	                       mul_q_lo,
 	                       coproc_read,
+	input  logic           high_vectors,
 
 `ifdef VERILATOR
 	input  word            insn,
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index c4f3772..3965114 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -6,24 +6,20 @@ module core_control_exception
 	             rst_n,
 
 	input  logic undefined,
+	             high_vectors,
 
 	output word  vector,
 	output logic exception
 );
 
-	logic high_vectors;
 	logic[2:0] vector_offset;
 
 	assign exception = undefined; //TODO
-	assign high_vectors = 0; //TODO
 	assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
 
 	always_comb
 		vector_offset = 3'b001; //TODO
 
-	//TODO: spsr_<mode> = cpsr
-	//TODO: actualizar modo
-	//TODO: deshabilitar IRQs/FIQs dependiendo de modo
 	//TODO: Considerar que data abort usa + 8, no + 4
 
 endmodule
diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
index f924c21..8ddc474 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/cp15/cp15.sv
@@ -1,5 +1,6 @@
-`include "core/uarch.sv"
 `include "core/cp15/map.sv"
+`include "core/mmu/format.sv"
+`include "core/uarch.sv"
 
 module core_cp15
 (
@@ -9,7 +10,10 @@ module core_cp15
 	input  coproc_decode dec,
 	input  word          write,
 
-	output word          read
+	output word          read,
+	output logic         high_vectors,
+	                     mmu_enable,
+	output mmu_base      mmu_ttbr
 );
 
 	logic load;
diff --git a/rtl/core/cp15/syscfg.sv b/rtl/core/cp15/syscfg.sv
index 599b682..d75f7ac 100644
--- a/rtl/core/cp15/syscfg.sv
+++ b/rtl/core/cp15/syscfg.sv
@@ -11,10 +11,12 @@ module core_cp15_syscfg
 	input  cp_opcode op2,
 	input  word      write,
 
-	output word      read
+	output word      read,
+	output logic     high_vectors,
+	                 mmu_enable
 );
 
-	logic mmu_enable, dcache_enable, icache_enable, high_vectors;
+	logic dcache_enable, icache_enable;
 
 	cp15_syscfg_ctrl ctrl, write_ctrl;
 
diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/cp15/ttbr.sv
index 622dd3f..5162edb 100644
--- a/rtl/core/cp15/ttbr.sv
+++ b/rtl/core/cp15/ttbr.sv
@@ -11,11 +11,11 @@ module core_cp15_ttbr
 	                 transfer,
 	input  word      write,
 
-	output word      read
+	output word      read,
+	output mmu_base  mmu_ttbr
 );
 
 	logic s, c;
-	mmu_base base;
 	cp15_ttbr read_ttbr, write_ttbr;
 	logic[1:0] rgn;
 
@@ -27,19 +27,19 @@ module core_cp15_ttbr
 	assign read_ttbr.sbz = 9'd0;
 	assign read_ttbr.rgn = rgn;
 	assign read_ttbr.imp = 0;
-	assign read_ttbr.base = base;
+	assign read_ttbr.base = mmu_ttbr;
 
 	always @(posedge clk or negedge rst_n)
 		if(!rst_n) begin
 			s <= 0;
 			c <= 0;
 			rgn <= 0;
-			base <= 0;
+			mmu_ttbr <= 0;
 		end else if(transfer && !load) begin
 			s <= write_ttbr.s;
 			c <= write_ttbr.c;
 			rgn <= write_ttbr.rgn;
-			base <= write_ttbr.base;
+			mmu_ttbr <= write_ttbr.base;
 		end
 
 endmodule