Split stall control logic out of control.sv

2 files changed, 50 insertions, 11 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index dee234e..5f7de3a 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -45,7 +45,7 @@ module core_control
 
 	ctrl_cycle cycle, next_cycle;
 
-	logic bubble, next_bubble, final_writeback, final_update_flags,
+	logic final_writeback, final_update_flags,
 	      ldst, ldst_pre, ldst_increment, ldst_writeback, pop_valid,
 	      data_snd_is_imm, data_snd_shift_by_reg, trivial_shift,
 	      undefined, exception, high_vectors;
@@ -58,7 +58,6 @@ module core_control
 	reg_list mem_regs, next_regs_upper, next_regs_lower;
 	ptr pc /*verilator public*/, next_pc_visible;
 
-	assign stall = next_cycle != ISSUE || next_bubble;
 	assign reg_mode = `MODE_SVC; //TODO
 	assign trivial_shift = shifter_shift == 0;
 	assign mem_data_wr = rd_value_b;
@@ -68,11 +67,12 @@ module core_control
 	assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
 	assign next_pc_visible = fetch_insn_pc + 2;
 
-	assign next_bubble =
-		   (final_writeback && final_rd == `R15)
-		|| ((dec.update_flags || dec.conditional) && (final_update_flags || update_flags))
-		|| (final_writeback && ((dec_data.uses_rn && (final_rd == dec_data.rn || dec_data.rn == `R15))
-		                      || final_rd == dec_snd.r || dec_snd.r == `R15));
+	logic bubble, next_bubble;
+
+	core_control_stall ctrl_stall
+	(
+		.*
+	);
 
 	core_control_ldst_pop ldst_pop
 	(
@@ -144,7 +144,6 @@ module core_control
 
 	always_ff @(posedge clk) begin
 		cycle <= next_cycle;
-		bubble <= 0;
 		branch <= 0;
 		writeback <= 0;
 		update_flags <= 0;
@@ -161,8 +160,6 @@ module core_control
 				final_writeback <= 0;
 				final_update_flags <= 0;
 
-				bubble <= next_bubble;
-
 				if(dec.execute & ~next_bubble) begin
 					branch <= dec_branch.branch;
 					branch_target <= next_pc_visible + dec_branch.offset;
@@ -275,7 +272,6 @@ module core_control
 
 	initial begin
 		cycle = ISSUE;
-		bubble = 0;
 
 		pc = 0;
 		pc_visible = 2;
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
new file mode 100644
index 0000000..c2f6a4d
--- /dev/null
+++ b/rtl/core/control/stall.sv
@@ -0,0 +1,43 @@
+`include "core/uarch.sv"
+
+module core_control_stall
+(
+	input  logic           clk,
+
+	input  datapath_decode dec,
+	input  data_decode     dec_data,
+	input  snd_decode      dec_snd,
+
+	input  ctrl_cycle      next_cycle,
+	input  logic           final_update_flags,
+	                       update_flags,
+	                       final_writeback,
+	                       writeback,
+	input  reg_num         final_rd,
+
+	output logic           stall,
+	                       bubble,
+	                       next_bubble
+);
+
+	logic pc_writeback_hazard, flags_hazard, data_hazard, rn_hazard,
+	      snd_hazard, flags_dependency, updating_flags;
+
+	assign stall = next_cycle != ISSUE || next_bubble;
+	assign next_bubble = pc_writeback_hazard || flags_hazard || data_hazard;
+
+	assign pc_writeback_hazard = final_writeback && final_rd == `R15;
+	assign flags_hazard = flags_dependency && updating_flags;
+	assign data_hazard = final_writeback && (rn_hazard || snd_hazard);
+	assign rn_hazard = dec_data.uses_rn && (final_rd == dec_data.rn || dec_data.rn == `R15);
+	assign snd_hazard = !dec_snd.is_imm && (dec_snd.r == final_rd || dec_snd.r == `R15);
+
+	assign flags_dependency = dec.update_flags || dec.conditional;
+	assign updating_flags = final_update_flags || update_flags;
+
+	always_ff @(posedge clk)
+		bubble <= next_cycle == ISSUE ? next_bubble : 0;
+
+	initial bubble = 0;
+
+endmodule