rtl/mp: fix design

3 files changed, 120 insertions, 83 deletions

diff --git a/rtl/mp.sv b/rtl/mp.sv
deleted file mode 100644
index a8ffee4..0000000
--- a/rtl/mp.sv
+++ /dev/null
@@ -1,83 +0,0 @@
-module mp
-(
-    input  logic clk,
-                 rst_n,
-    
-    // todas las señales de shutdown_request de otros procesadores
-    input  logic [1:0] avl_address,
-	input  logic       avl_read,
-	                   avl_write,
-	input  logic[31:0] avl_writedata,
-    output logic[31:0] avl_readdata,
-
-    input logic       cpu_halted_pe_0,
-                      cpu_halted_pe_1,
-                      cpu_halted_pe_2,
-                      cpu_halted_pe_3,
-	input logic       breakpoint_pe_0,
-                      breakpoint_pe_1,
-                      breakpoint_pe_2,
-                      breakpoint_pe_3,    
-
-    // señales de halt 
-    output logic      halt_pe_0,
-                      halt_pe_1,
-                      halt_pe_2,
-                      halt_pe_3,
-                      step_pe_0,
-                      step_pe_1,
-                      step_pe_2,
-                      step_pe_3
-);
-
-    logic[7:0] pe_status;
-    logic halt, step, run;
-
-    assign {step, run, halt} = avl_writedata[2:0];
-    assign avl_readdata = {24'b0, pe_status};
-
-    always @(posedge clk or negedge rst_n)
-        if(!rst_n) begin
-            halt_pe_0 <= 0; //Encender solo el PE0
-            halt_pe_1 <= 1;
-            halt_pe_2 <= 1;
-            halt_pe_3 <= 1;
-            step_pe_1 <= 0;
-            step_pe_2 <= 0;
-            step_pe_3 <= 0;
-            step_pe_4 <= 0;
-            pe_status <= {($bits(pe_status)){1'b0}};
-        end else begin
-
-            pe_status <= { cpu_halted_pe_0,
-        	               breakpoint_pe_0,
-                           cpu_halted_pe_1,
-                           breakpoint_pe_1,
-                           cpu_halted_pe_2,
-                           breakpoint_pe_2,
-                           cpu_halted_pe_3,
-                           breakpoint_pe_3 };
-
-            unique case(avl_address)
-                2'b00: begin
-                    //Se hace halt hasta el siguiente ciclo después de que se 
-                    //solicita el breakpoint
-                    halt_pe_0 <= (halt_pe_0 || halt || breakpoint_pe_0) && !run && !step;
-                    step_pe_0 <= !breakpoint_pe_0 || step;
-                end
-                2'b01: begin
-                    halt_pe_1 <= ((halt_pe_1 || halt) && !run) || breakpoint_pe_1 || !step;
-                    step_pe_1 <= !breakpoint_pe_1 || step;
-                end
-                2'b10: begin
-                    halt_pe_2 <= ((halt_pe_2 || halt) && !run) || breakpoint_pe_2 || !step;
-                    step_pe_2 <= !breakpoint_pe_2 || step;
-                end
-                2'b11: begin
-                    halt_pe_3 <= ((halt_pe_3 || halt) && !run) || breakpoint_pe_3 || !step;
-                    step_pe_3 <= !breakpoint_pe_3 || step;
-                end      
-            endcase
-        end
-
-endmodule
\ No newline at end of file
diff --git a/rtl/mp/mp_ctrl.sv b/rtl/mp/mp_ctrl.sv
new file mode 100644
index 0000000..362e450
--- /dev/null
+++ b/rtl/mp/mp_ctrl.sv
@@ -0,0 +1,73 @@
+module mp_ctrl
+(
+	input  logic	   clk,
+	                   rst_n,
+	
+	input  logic       avl_read,
+	                   avl_write,
+	input  logic[31:0] avl_writedata,
+	output logic[31:0] avl_readdata,
+
+	input logic        cpu_halted_0,
+	                   cpu_halted_1,
+	                   cpu_halted_2,
+	                   cpu_halted_3,
+	input logic        breakpoint_0,
+	                   breakpoint_1,
+	                   breakpoint_2,
+	                   breakpoint_3,	
+
+	output logic       halt_0,
+	                   halt_1,
+	                   halt_2,
+	                   halt_3,
+	                   step_0,
+	                   step_1,
+	                   step_2,
+	                   step_3
+);
+
+	logic write;
+	logic[7:0] readdata_3, readdata_2, readdata_1, readdata_0,
+	           writedata_3, writedata_2, writedata_1, writedata_0;
+
+	assign avl_readdata = {readdata_3, readdata_2, readdata_1, readdata_0};
+	assign {writedata_3, writedata_2, writedata_1, writedata_0} = avl_writedata;
+
+	// No hay addresses
+	assign write = avl_write;
+
+	mp_pe pe_1
+	(
+		.step(step_1),
+		.halt(halt_1),
+		.cpu_halted(cpu_halted_1),
+		.breakpoint(breakpoint_1),
+		.readdata(readdata_1),
+		.writedata(writedata_1),
+		.*
+	);
+
+	mp_pe pe_2
+	(
+		.step(step_2),
+		.halt(halt_2),
+		.cpu_halted(cpu_halted_2),
+		.breakpoint(breakpoint_2),
+		.readdata(readdata_2),
+		.writedata(writedata_2),
+		.*
+	);
+
+	mp_pe pe_3
+	(
+		.step(step_3),
+		.halt(halt_3),
+		.cpu_halted(cpu_halted_3),
+		.breakpoint(breakpoint_3),
+		.readdata(readdata_3),
+		.writedata(writedata_3),
+		.*
+	);
+
+endmodule
diff --git a/rtl/mp/pe.sv b/rtl/mp/pe.sv
new file mode 100644
index 0000000..f50ed2f
--- /dev/null
+++ b/rtl/mp/pe.sv
@@ -0,0 +1,47 @@
+module mp_pe
+#(parameter IS_BSP=0)
+(
+	input  logic	  clk,
+	                  rst_n,
+	
+	input  logic      write,
+	input  logic[7:0] writedata,
+	output logic[7:0] readdata,
+
+	input logic       cpu_halted,
+	                  breakpoint,
+
+	output logic      halt,
+	                  step
+);
+
+	struct packed
+	{
+		logic step, halt, run;
+	} req;
+
+	struct packed
+	{
+		logic breakpoint, cpu_halted;
+	} status;
+
+	assign req = writedata[$bits(req) - 1:0];
+	assign readdata = {{(8 - $bits(status)){1'b0}}, status};
+
+	always @(posedge clk or negedge rst_n)
+		if (!rst_n) begin
+			halt <= IS_BSP ? 0 : 1; // Boot es single-core
+			step <= 0;
+			status <= {($bits(status)){1'b0}};
+		end else begin
+			status.breakpoint <= breakpoint;
+			status.cpu_halted <= cpu_halted;
+
+			//Se hace halt hasta el siguiente ciclo después de que se 
+			//solicita el breakpoint
+			step <= !breakpoint || (req.step && write);
+			halt <= (halt || breakpoint || (req.halt && write))
+			     && !((req.run || req.step) && write);
+		end
+
+endmodule