Quartus has not support for unique0

8 files changed, 14 insertions, 13 deletions

diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv
index fdf4ebe..f6bc517 100644
--- a/rtl/core/control/cycles.sv
+++ b/rtl/core/control/cycles.sv
@@ -23,7 +23,7 @@ module core_control_cycles
 	always_comb begin
 		next_cycle = ISSUE;
 
-		unique0 case(cycle)
+		unique case(cycle)
 			ISSUE:
 				if(exception)
 					next_cycle = EXCEPTION;
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index 4965ec3..5fa6db9 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -65,7 +65,7 @@ module core_control_data
 	end
 
 	always_ff @(posedge clk)
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				if(issue) begin
 					alu <= dec_data.op;
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index daea893..0a2f6c9 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -45,7 +45,7 @@ module core_control_ldst
 	);
 
 	always_ff @(posedge clk)
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				if(issue) begin
 					// TODO: dec_ldst.unprivileged/user_regs
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
index 81fc120..c3625f8 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul.sv
@@ -35,7 +35,7 @@ module core_control_mul
 	always_ff @(posedge clk) begin
 		mul_start <= 0;
 
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				if(issue) begin
 					mul <= dec.mul;
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 46a16d7..cedf3cf 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -27,7 +27,7 @@ module core_control_select
 	assign reg_mode = `MODE_SVC; //TODO
 
 	always_ff @(posedge clk)
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				if(issue) begin
 					ra <= dec_data.rn;
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 6a0afc8..733881c 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -38,7 +38,7 @@ module core_control_writeback
 	always_ff @(posedge clk) begin
 		wb_alu_flags <= alu_flags;
 
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			TRANSFER:
 				if(mem_ready)
 					rd <= final_rd;
@@ -53,7 +53,7 @@ module core_control_writeback
 				rd <= mul_r_add_hi;
 		endcase
 
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				if(issue)
 					final_rd <= dec_data.rd;
@@ -70,7 +70,7 @@ module core_control_writeback
 		endcase
 
 		writeback <= 0;
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				writeback <= final_writeback;
 
@@ -84,7 +84,7 @@ module core_control_writeback
 				writeback <= 1;
 		endcase
 
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				final_writeback <= issue && dec.writeback;
 
@@ -93,7 +93,7 @@ module core_control_writeback
 		endcase
 
 		update_flags <= 0;
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				update_flags <= final_update_flags;
 
@@ -101,7 +101,7 @@ module core_control_writeback
 				final_update_flags <= 0;
 		endcase
 
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			ISSUE:
 				final_update_flags <= issue && dec_psr.update_flags;
 
@@ -123,7 +123,7 @@ module core_control_writeback
 				wr_value <= q_alu;
 		endcase
 
-		unique0 case(next_cycle)
+		unique case(next_cycle)
 			TRANSFER:
 				if(mem_ready)
 					wr_value <= mem_data_rd;
diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv
index e68729d..9d86f9e 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/decode/mux.sv
@@ -77,6 +77,7 @@ module core_decode_mux
 		undefined = cond_undefined;
 		writeback = 0;
 		conditional = explicit_cond;
+		restore_spsr = 0;
 
 		spsr = 0;
 		psr_write = 0;
diff --git a/rtl/core/psr.sv b/rtl/core/psr.sv
index 02d8f81..0bccfb7 100644
--- a/rtl/core/psr.sv
+++ b/rtl/core/psr.sv
@@ -129,7 +129,7 @@ module core_psr
 		end else if(!saved)
 			cpsr <= wr_clean;
 		else
-			unique0 case(mode)
+			unique case(mode)
 				`MODE_SVC: spsr_svc <= wr_clean;
 				`MODE_ABT: spsr_abt <= wr_clean;
 				`MODE_UND: spsr_und <= wr_clean;