Split ALU/shifter control logic out of control.sv

3 files changed, 126 insertions, 90 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 0912387..fa4510c 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -55,24 +55,19 @@ module core_control
 );
 
 	logic final_update_flags, ldst, ldst_pre, ldst_increment,
-	      ldst_writeback, pop_valid, data_snd_is_imm, data_snd_shift_by_reg,
-	      trivial_shift, undefined, exception, high_vectors;
+	      ldst_writeback, pop_valid, exception, high_vectors;
 
 	logic[2:0] vector_offset;
-	logic[5:0] data_shift_imm;
-	logic[11:0] data_imm;
-	word saved_base, mem_offset, vector;
+	word mem_offset, vector;
 	reg_num r_shift, popped_upper, popped_lower, popped;
 	reg_list mem_regs, next_regs_upper, next_regs_lower;
 
 	assign reg_mode = `MODE_SVC; //TODO
-	assign trivial_shift = shifter_shift == 0;
 	assign mem_data_wr = rd_value_b;
 	assign popped = ldst_increment ? popped_lower : popped_upper;
 	assign exception = undefined; //TODO
 	assign high_vectors = 0; //TODO
 	assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
-	assign next_pc_visible = fetch_insn_pc + 2;
 
 	ctrl_cycle cycle, next_cycle;
 
@@ -89,7 +84,7 @@ module core_control
 	);
 
 	ptr pc /*verilator public*/, next_pc_visible;
-	logic issue;
+	logic issue, undefined;
 
 	core_control_issue ctrl_issue
 	(
@@ -111,7 +106,10 @@ module core_control
 		.*
 	);
 
-	core_control_mux ctrl_mux
+	word saved_base;
+	logic trivial_shift, data_snd_shift_by_reg;
+
+	core_control_data ctrl_data
 	(
 		.*
 	);
@@ -136,22 +134,9 @@ module core_control
 				final_update_flags <= 0;
 
 				if(issue) begin
-					alu <= dec_data.op;
 					ra <= dec_data.rn;
-
-					data_snd_is_imm <= dec_snd.is_imm;
-					data_snd_shift_by_reg <= dec_snd.shift_by_reg;
-					data_imm <= dec_snd.imm;
-					data_shift_imm <= dec_snd.shift_imm;
-
-					shifter.shr <= dec_snd.shr;
-					shifter.ror <= dec_snd.ror;
-					shifter.put_carry <= dec_snd.put_carry;
-					shifter.sign_extend <= dec_snd.sign_extend;
-
 					rb <= dec_snd.r;
 					r_shift <= dec_snd.r_shift;
-					c_in <= flags.c;
 
 					// TODO: dec_ldst.unprivileged/user_regs
 					// TODO: byte/halfword sizes
@@ -176,16 +161,10 @@ module core_control
 				update_flags <= final_update_flags;
 			end
 
-			RD_INDIRECT_SHIFT: begin
+			RD_INDIRECT_SHIFT:
 				rb <= r_shift;
-				data_snd_shift_by_reg <= 0;
-				saved_base <= rd_value_b;
-			end
 
-			WITH_SHIFT: begin
-				c_in <= c_shifter;
-				saved_base <= q_shifter;
-			end
+			WITH_SHIFT: ;
 
 			TRANSFER: begin
 				if(cycle != TRANSFER) begin
@@ -196,7 +175,6 @@ module core_control
 				if(cycle != TRANSFER || mem_ready) begin
 					mem_regs <= ldst_increment ? next_regs_lower : next_regs_upper;
 					mem_addr <= ldst_pre ? q_alu[31:2] : alu_a[31:2];
-					saved_base <= q_alu;
 
 					if(pop_valid)
 						rb <= popped;
@@ -209,24 +187,16 @@ module core_control
 
 			BASE_WRITEBACK: ;
 
-			EXCEPTION: begin
+			EXCEPTION:
 				//TODO: spsr_<mode> = cpsr
 				//TODO: actualizar modo
 				//TODO: deshabilitar IRQs/FIQs dependiendo de modo
 				//TODO: Considerar que data abort usa + 8, no + 4
-				alu <= `ALU_ADD;
-				data_imm <= 12'd4;
-				data_snd_is_imm <= 1;
-
 				final_update_flags <= 0;
-			end
 		endcase
 	end
 
 	initial begin
-		c_in = 0;
-		data_snd_shift_by_reg = 0;
-
 		wb_alu_flags = 4'b0000;
 
 		ldst = 0;
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
new file mode 100644
index 0000000..cc83336
--- /dev/null
+++ b/rtl/core/control/data.sv
@@ -0,0 +1,116 @@
+`include "core/uarch.sv"
+
+module core_control_data
+(
+	input  logic           clk,
+
+	input  data_decode     dec_data,
+	input  snd_decode      dec_snd,
+	input  word            rd_value_a,
+	                       rd_value_b,
+	input  logic           mem_ready,
+	input  word            q_alu,
+	                       q_shifter,
+	input  logic           c_shifter,
+
+	input  ctrl_cycle      cycle,
+	                       next_cycle,
+	input  logic           issue,
+	input  ptr             pc,
+	input  word            mem_offset,
+	input  psr_flags       flags,
+
+	output alu_op          alu,
+	output word            alu_a,
+	                       alu_b,
+	                       saved_base,
+	output shifter_control shifter,
+	output logic[7:0]      shifter_shift,
+	output logic           c_in,
+	                       trivial_shift,
+	                       data_snd_shift_by_reg
+);
+
+	logic data_snd_is_imm;
+	logic[5:0] data_shift_imm;
+	logic[11:0] data_imm;
+
+	assign trivial_shift = shifter_shift == 0;
+
+	always_comb begin
+		unique case(cycle)
+			RD_INDIRECT_SHIFT: shifter_shift = rd_value_b[7:0];
+			default:           shifter_shift = {2'b00, data_shift_imm};
+		endcase
+
+		unique case(cycle)
+			TRANSFER:  alu_a = saved_base;
+			EXCEPTION: alu_a = {pc, 2'b00};
+			default:   alu_a = rd_value_a;
+		endcase
+
+		unique case(cycle)
+			RD_INDIRECT_SHIFT, WITH_SHIFT:
+				alu_b = saved_base;
+
+			TRANSFER:
+				alu_b = mem_offset;
+
+			default:
+				if(data_snd_is_imm)
+					alu_b = {{20{1'b0}}, data_imm};
+				else
+					alu_b = rd_value_b;
+		endcase
+	end
+
+	always @(posedge clk)
+		unique0 case(next_cycle)
+			ISSUE:
+				if(issue) begin
+					alu <= dec_data.op;
+					c_in <= flags.c;
+
+					data_snd_is_imm <= dec_snd.is_imm;
+					data_snd_shift_by_reg <= dec_snd.shift_by_reg;
+					data_imm <= dec_snd.imm;
+					data_shift_imm <= dec_snd.shift_imm;
+
+					shifter.shr <= dec_snd.shr;
+					shifter.ror <= dec_snd.ror;
+					shifter.put_carry <= dec_snd.put_carry;
+					shifter.sign_extend <= dec_snd.sign_extend;
+				end
+
+			RD_INDIRECT_SHIFT: begin
+				saved_base <= rd_value_b;
+				data_snd_shift_by_reg <= 0;
+			end
+
+			WITH_SHIFT: begin
+				c_in <= c_shifter;
+				saved_base <= q_shifter;
+			end
+
+			TRANSFER:
+				if(cycle != TRANSFER || mem_ready)
+					saved_base <= q_alu;
+
+			EXCEPTION: begin
+				alu <= `ALU_ADD;
+				data_imm <= 12'd4;
+				data_snd_is_imm <= 1;
+			end
+		endcase
+
+	initial begin
+		alu = {$bits(alu){1'b0}};
+		c_in = 0;
+		shifter = {$bits(shifter){1'b0}};
+		data_imm = {$bits(data_imm){1'b0}};
+		data_shift_imm = {$bits(data_shift_imm){1'b0}};
+		data_snd_is_imm = 0;
+		data_snd_shift_by_reg = 0;
+	end
+
+endmodule
diff --git a/rtl/core/control/mux.sv b/rtl/core/control/mux.sv
deleted file mode 100644
index 58d2197..0000000
--- a/rtl/core/control/mux.sv
+++ /dev/null
@@ -1,50 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_mux
-(
-	input  logic       clk,
-
-	input  word        rd_value_a,
-	                   rd_value_b,
-
-	input  ctrl_cycle  cycle,
-	input  logic       data_snd_is_imm,
-	input  logic[5:0]  data_shift_imm,
-	input  logic[11:0] data_imm,
-	input  ptr         pc,
-	input  word        saved_base,
-	                   mem_offset,
-
-	output word        alu_a,
-	                   alu_b,
-	output logic[7:0]  shifter_shift
-);
-
-	always_comb begin
-		unique case(cycle)
-			RD_INDIRECT_SHIFT: shifter_shift = rd_value_b[7:0];
-			default:           shifter_shift = {2'b00, data_shift_imm};
-		endcase
-
-		unique case(cycle)
-			TRANSFER:  alu_a = saved_base;
-			EXCEPTION: alu_a = {pc, 2'b00};
-			default:   alu_a = rd_value_a;
-		endcase
-
-		unique case(cycle)
-			RD_INDIRECT_SHIFT, WITH_SHIFT:
-				alu_b = saved_base;
-
-			TRANSFER:
-				alu_b = mem_offset;
-
-			default:
-				if(data_snd_is_imm)
-					alu_b = {{20{1'b0}}, data_imm};
-				else
-					alu_b = rd_value_b;
-		endcase
-	end
-
-endmodule