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authorAlejandro Soto <alejandro@34project.org>2022-12-07 20:59:22 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-07 20:59:22 -0600
commitd6fff0eb1ce867192d30babb839fc09c30049f0b (patch)
tree9d3b5fab4ccaae51d8f5b44a2b5610507b13638e /rtl
parentd8d687ad8052809f66c0b5a36d4ca74d0a3b202c (diff)
Fix register-indirect shifts
Diffstat (limited to 'rtl')
-rw-r--r--rtl/core/control/select.sv4
1 files changed, 3 insertions, 1 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 1ea2c31..0ab7bb2 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -29,7 +29,9 @@ module core_control_select
if(next_cycle.issue) begin
ra = dec.data.rn;
rb = dec.snd.r;
- end else if(next_cycle.transfer) begin
+ end else if(next_cycle.rd_indirect_shift)
+ rb = r_shift;
+ else if(next_cycle.transfer) begin
if(ldst_next)
// final_rd viene de dec.ldst.rd
rb = pop_valid ? popped : final_rd;