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| author | Alejandro Soto <alejandro@34project.org> | 2022-10-17 01:14:56 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-17 01:14:56 -0600 |
| commit | b328dee91da704474509054043740128e5969c8b (patch) | |
| tree | ed71f8d2678043213facd0623b0e57f69bf3535e /rtl | |
| parent | cf3fa9d250dcbc3d0aa0c688a62902f96e195053 (diff) | |
Use negative clock edge for register file in Verilator builds
Diffstat (limited to 'rtl')
| -rw-r--r-- | rtl/core/regs/file.sv | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv index 7109edf..e0f9b4c 100644 --- a/rtl/core/regs/file.sv +++ b/rtl/core/regs/file.sv @@ -14,7 +14,12 @@ module core_reg_file // Ver comentario en uarch.sv word file[30] /*verilator public*/; + //FIXME: Esto claramente no sirve +`ifdef VERILATOR + always_ff @(negedge clk) begin +`else always_ff @(posedge clk) begin +`endif if(wr_enable) file[wr_index] <= wr_value; |