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authorAlejandro Soto <alejandro@34project.org>2022-11-02 23:13:01 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-02 23:13:01 -0600
commitfe7ae05a9acbc237e386e9841d63e12c4f5aae42 (patch)
tree714dc285f0d39ab27da10629b3efdb39e89f6469 /rtl
parent67f85b9f827badd1e588a33671c821a99fb0a80b (diff)
Add new toplevel signals
Diffstat (limited to '')
-rw-r--r--rtl/top/conspiracion.sv19
1 files changed, 17 insertions, 2 deletions
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 50b9cd8..940e46a 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -16,7 +16,17 @@ module conspiracion
inout wire memory_mem_dqs_n,
output wire memory_mem_odt,
output wire memory_mem_dm,
- input wire memory_oct_rzqin
+ input wire memory_oct_rzqin,
+ output wire [12:0] vram_wire_addr,
+ output wire [1:0] vram_wire_ba,
+ output wire vram_wire_cas_n,
+ output wire vram_wire_cke,
+ output wire vram_wire_cs_n,
+ inout wire [15:0] vram_wire_dq,
+ output wire [1:0] vram_wire_dqm,
+ output wire vram_wire_ras_n,
+ output wire vram_wire_we_n
+
);
//TODO
@@ -25,7 +35,7 @@ module conspiracion
logic[29:0] addr;
logic[31:0] data_rd, data_wr;
- logic ready, write, start;
+ logic clk_core, ready, write, start;
arm810 core
(
@@ -38,6 +48,9 @@ module conspiracion
.bus_start(start)
);
+ //TODO: pio_0_external_connection_export,
+ //TODO: pll_0_outclk3_clk,
+
platform plat
(
.master_0_core_addr(addr),
@@ -46,6 +59,8 @@ module conspiracion
.master_0_core_ready(ready),
.master_0_core_write(write),
.master_0_core_start(start),
+ .pll_0_outclk3_clk(),
+ .pio_0_external_connection_export(),
.*
);