rtl/if_common: add id, resp, size, strb signals to if_axib

2 files changed, 91 insertions, 37 deletions

diff --git a/rtl/gfx/gfx_shader_front.sv b/rtl/gfx/gfx_shader_front.sv
index 0a2b8b8..3398e52 100644
--- a/rtl/gfx/gfx_shader_front.sv
+++ b/rtl/gfx/gfx_shader_front.sv
@@ -122,14 +122,23 @@ import gfx::*;
 	group_id groups[BIND_STAGES];
 	icache_line_tag araddr, request_addr;
 
-	assign mem.bready = 0;
-	assign mem.wvalid = 0;
-	assign mem.awvalid = 0;
-
+	assign mem.arid = '0;
 	assign mem.arlen = ($bits(mem.arlen))'($bits(oword) / $bits(word) - 1);
+	assign mem.arsize = 3'b101; // 32 bits/beat
 	assign mem.araddr = {araddr, ($clog2($bits(oword)) - $clog2($bits(word)) + SUBWORD_BITS)'('0)};
 	assign mem.arburst = 2'b01; // Incremental mode
 
+	assign mem.awid = '0;
+	assign mem.awlen = mem.arlen;
+	assign mem.awsize = mem.arsize;
+	assign mem.awburst = mem.arburst;
+	assign mem.awvalid = 0;
+
+	assign mem.wstrb = '0;
+	assign mem.wvalid = 0;
+
+	assign mem.bready = 0;
+
 	assign runnable_in.tx.data = loop_group;
 	assign runnable_in.tx.valid = loop_valid;
 
diff --git a/rtl/if_common/if_axib.sv b/rtl/if_common/if_axib.sv
index 6db8518..3d703de 100644
--- a/rtl/if_common/if_axib.sv
+++ b/rtl/if_common/if_axib.sv
@@ -1,80 +1,125 @@
-// AXI4 con burst
+// AXI4 full modulo prot, cache, lock, QoS, region
 interface if_axib
-#(int WIDTH = 32);
+#(int ADDR_WIDTH = 32,
+  int DATA_WIDTH = 32,
+  int ID_WIDTH   = 8);
 
-	logic              awvalid,
-	                   awready;
-	logic[7:0]         awlen;
-	logic[1:0]         awburst;
-	logic[WIDTH - 1:0] awaddr;
+	logic                   awvalid,
+	                        awready;
+	logic[ID_WIDTH - 1:0]   awid;
+	logic[7:0]              awlen;
+	logic[2:0]              awsize;
+	logic[1:0]              awburst;
+	logic[ADDR_WIDTH - 1:0] awaddr;
 
-	logic              wlast;
-	logic              wvalid;
-	logic              wready;
-	logic[WIDTH - 1:0] wdata;
+	logic                             wvalid;
+	logic                             wready;
+	logic[DATA_WIDTH - 1:0]           wdata;
+	logic                             wlast;
+	logic[(DATA_WIDTH + 7) / 8 - 1:0] wstrb;
 
-	logic bvalid;
-	logic bready;
+	logic                 bvalid;
+	logic                 bready;
+	logic[ID_WIDTH - 1:0] bid;
+	logic[1:0]            bresp;
 
-	logic              arvalid,
-	                   arready;
-	logic[7:0]         arlen;
-	logic[1:0]         arburst;
-	logic[WIDTH - 1:0] araddr;
+	logic                   arvalid,
+	                        arready;
+	logic[ID_WIDTH - 1:0]   arid;
+	logic[7:0]              arlen;
+	logic[2:0]              arsize;
+	logic[1:0]              arburst;
+	logic[ADDR_WIDTH - 1:0] araddr;
 
-	logic              rlast;
-	logic              rvalid;
-	logic              rready;
-	logic[WIDTH - 1:0] rdata;
+	logic                   rvalid;
+	logic                   rready;
+	logic[ID_WIDTH - 1:0]   rid;
+	logic[DATA_WIDTH - 1:0] rdata;
+	logic[1:0]              rresp;
+	logic                   rlast;
 
 	modport m
 	(
 		input  awready,
+
 		       wready,
+
+		       bid,
+		       bresp,
 		       bvalid,
+
 		       arready,
+
+		       rid,
+		       rdata,
 		       rlast,
+		       rresp,
 		       rvalid,
-		       rdata,
 
-		output awlen,
+		output awid,
+		       awlen,
+		       awaddr,
+		       awsize,
 		       awburst,
 		       awvalid,
-		       awaddr,
+
+		       wdata,
 		       wlast,
+		       wstrb,
 		       wvalid,
-		       wdata,
+
 		       bready,
+
+		       arid,
 		       arlen,
+		       araddr,
+		       arsize,
 		       arburst,
 		       arvalid,
-		       araddr,
+
 		       rready
 	);
 
 	modport s
 	(
-		input  awlen,
+		input  awid,
+		       awlen,
+		       awaddr,
+		       awsize,
 		       awburst,
 		       awvalid,
-		       awaddr,
+
+		       wdata,
 		       wlast,
+		       wstrb,
 		       wvalid,
-		       wdata,
+
 		       bready,
+
+		       arid,
 		       arlen,
+		       araddr,
+		       arsize,
 		       arburst,
 		       arvalid,
-		       araddr,
+
 		       rready,
 
 		output awready,
+
 		       wready,
+
+		       bid,
+		       bresp,
 		       bvalid,
+
 		       arready,
+
+		       rid,
+		       rdata,
 		       rlast,
-		       rvalid,
-		       rdata
+		       rresp,
+		       rvalid
 	);
 
 endinterface