Refactor CPSR and uarch.sv

11 files changed, 44 insertions, 37 deletions

diff --git a/rtl/core/alu/alu.sv b/rtl/core/alu/alu.sv
index 4d0a9cc..ade0340 100644
--- a/rtl/core/alu/alu.sv
+++ b/rtl/core/alu/alu.sv
@@ -1,4 +1,3 @@
-`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_alu
diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 9a99168..b37057d 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -1,4 +1,3 @@
-`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module arm810
@@ -52,7 +51,6 @@ module arm810
 	ptr branch_target;
 	psr_mode reg_mode;
 	alu_op data_op;
-	psr_flags flags, next_flags;
 
 	core_cycles cycles
 	(
@@ -60,6 +58,13 @@ module arm810
 		.*
 	);
 
+	psr_flags flags, next_flags;
+
+	core_psr psr
+	(
+		.*
+	);
+
 	logic wr_pc;
 	word wr_value, rd_value_a, rd_value_b;
 
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index c5ad62f..0f6ce15 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -1,4 +1,3 @@
-`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_cycles
@@ -11,7 +10,6 @@ module core_cycles
 	input  ptr       decode_branch_offset,
 	input  alu_op    decode_data_op,
 	input  ptr       fetch_insn_pc,
-	input  psr_flags alu_flags,
 
 	output logic     stall,
 	                 branch,
@@ -21,9 +19,7 @@ module core_cycles
 	                 pc,
 	                 pc_visible,
 	output psr_mode  reg_mode,
-	output alu_op    data_op,
-	output psr_flags flags,
-	                 next_flags
+	output alu_op    data_op
 );
 
 	enum
@@ -34,12 +30,10 @@ module core_cycles
 	assign stall = next_cycle != EXECUTE;
 	assign pc_visible = pc + 2;
 	assign next_cycle = EXECUTE; //TODO
-	assign next_flags = alu_flags; //TODO
 	assign reg_mode = `MODE_SVC; //TODO
 
 	always_ff @(posedge clk) begin
 		cycle <= next_cycle;
-		flags <= next_flags;
 
 		if(next_cycle == EXECUTE) begin
 			branch <= 0;
diff --git a/rtl/core/decode/conds.sv b/rtl/core/decode/conds.sv
index 3eef925..652760d 100644
--- a/rtl/core/decode/conds.sv
+++ b/rtl/core/decode/conds.sv
@@ -1,5 +1,5 @@
 `include "core/isa.sv"
-`include "core/psr.sv"
+`include "core/uarch.sv"
 
 module core_decode_conds
 (
diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data.sv
index 51370be..e132975 100644
--- a/rtl/core/decode/data.sv
+++ b/rtl/core/decode/data.sv
@@ -1,5 +1,4 @@
 `include "core/isa.sv"
-`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_decode_data
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 508467d..6b9b3b5 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -1,5 +1,4 @@
 `include "core/isa.sv"
-`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_decode
diff --git a/rtl/core/isa.sv b/rtl/core/isa.sv
index 710b11b..1778d33 100644
--- a/rtl/core/isa.sv
+++ b/rtl/core/isa.sv
@@ -4,11 +4,6 @@
 `define FIELD_COND [31:28]
 `define FIELD_OP   [27:0]
 
-typedef logic[3:0] reg_num;
-
-`define R14 4'b1110
-`define R15 4'b1111
-
 `define COND_EQ 4'b0000
 `define COND_NE 4'b0001
 `define COND_HS 4'b0010
diff --git a/rtl/core/psr.sv b/rtl/core/psr.sv
index 1450333..0ade723 100644
--- a/rtl/core/psr.sv
+++ b/rtl/core/psr.sv
@@ -1,19 +1,19 @@
-`ifndef CORE_PSR_SV
-`define CORE_PSR_SV
+`include "core/uarch.sv"
 
-typedef struct packed
-{
-	logic n, z, c, v;
-} psr_flags;
+module core_psr
+(
+	input  logic     clk,
+	input  psr_flags alu_flags,
 
-typedef logic[4:0] psr_mode;
+	output psr_flags flags,
+	                 next_flags
+);
 
-`define MODE_USR 5'b10000
-`define MODE_FIQ 5'b10001
-`define MODE_IRQ 5'b10010
-`define MODE_SVC 5'b10011
-`define MODE_ABT 5'b10111
-`define MODE_UND 5'b11011
-`define MODE_SYS 5'b11111
+	assign next_flags = alu_flags; //TODO
 
-`endif
+	always_ff @(posedge clk)
+		flags <= next_flags;
+
+	initial flags = 4'b0000;
+
+endmodule
diff --git a/rtl/core/regs/map.sv b/rtl/core/regs/map.sv
index b4da988..11085d4 100644
--- a/rtl/core/regs/map.sv
+++ b/rtl/core/regs/map.sv
@@ -1,5 +1,3 @@
-`include "core/isa.sv"
-`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_reg_map
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index 5f51faa..182b240 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -1,5 +1,4 @@
-`include "core/isa.sv"
-`include "core/psr.sv"
+`include "core/uarch.sv"
 
 module core_regs
 (
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index be67bd5..07b479d 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -4,9 +4,13 @@
 // Decodifica como andeq r0, r0, r0
 `define NOP 32'd0
 
+typedef logic[3:0]  reg_num;
 typedef logic[31:0] word;
 typedef logic[29:0] ptr;
 
+`define R14 4'b1110
+`define R15 4'b1111
+
 /* Se necesitan 30 GPRs. De A2.3:
  *
  *   The ARM processor has a total of 37 registers:
@@ -37,4 +41,19 @@ typedef logic[3:0] alu_op;
 `define ALU_BIC 4'b1110
 `define ALU_MVN 4'b1111
 
+typedef struct packed
+{
+	logic n, z, c, v;
+} psr_flags;
+
+typedef logic[4:0] psr_mode;
+
+`define MODE_USR 5'b10000
+`define MODE_FIQ 5'b10001
+`define MODE_IRQ 5'b10010
+`define MODE_SVC 5'b10011
+`define MODE_ABT 5'b10111
+`define MODE_UND 5'b11011
+`define MODE_SYS 5'b11111
+
 `endif