Register decode output in a new porch stage

8 files changed, 94 insertions, 44 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 3f2a53c..07a397b 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -13,26 +13,39 @@ module arm810
 	output word  bus_data_wr
 );
 
-	logic stall, prefetch_flush, insn_start;
-	word insn;
 	ptr fetch_insn_pc, insn_addr;
+	word fetch_insn;
+	logic stall, flush, prefetch_flush, insn_start;
+
+	//TODO
+	assign prefetch_flush = 0;
 
 	core_fetch #(.PREFETCH_ORDER(2)) fetch
 	(
-		.branch(explicit_branch || wr_pc),
-		.flush(0), //TODO
 		.addr(insn_addr),
-		.fetched(insn_ready),
-		.fetch_data(insn_data_rd),
+		.insn(fetch_insn),
 		.fetch(insn_start),
+		.branch(explicit_branch || wr_pc),
+		.fetched(insn_ready),
 		.insn_pc(fetch_insn_pc),
+		.fetch_data(insn_data_rd),
 		.*
 	);
 
-	insn_decode dec;
+	insn_decode fetch_dec;
 
 	core_decode decode
 	(
+		.dec(fetch_dec),
+		.insn(fetch_insn)
+	);
+
+	ptr insn_pc;
+	word insn;
+	insn_decode dec;
+
+	core_porch porch
+	(
 		.*
 	);
 
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 4ea590a..077ba1c 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -4,7 +4,7 @@ module core_control
 (
 	input  logic           clk,
 	input  insn_decode     dec,
-	input  ptr             fetch_insn_pc,
+	input  ptr             insn_pc,
 	input  psr_flags       flags,
 	                       alu_flags,
 	input  word            rd_value_a,
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index 5ed03f0..e3644c4 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -5,7 +5,7 @@ module core_control_issue
 	input  logic       clk,
 
 	input  insn_decode dec,
-	input  ptr         fetch_insn_pc,
+	input  ptr         insn_pc,
 
 	input  ctrl_cycle  next_cycle,
 	input  logic       next_bubble,
@@ -22,7 +22,7 @@ module core_control_issue
 );
 
 	assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
-	assign next_pc_visible = fetch_insn_pc + 2;
+	assign next_pc_visible = insn_pc + 2;
 
 	always_ff @(posedge clk)
 		if(next_cycle == ISSUE) begin
@@ -30,10 +30,10 @@ module core_control_issue
 
 `ifdef VERILATOR
 			if(dec.ctrl.undefined)
-				$display("[core] undefined insn: [0x%08x] %08x", fetch_insn_pc << 2, insn);
+				$display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn);
 `endif
 
-			pc <= fetch_insn_pc;
+			pc <= insn_pc;
 			pc_visible <= next_pc_visible;
 		end
 
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index ab8d2b9..6c5b802 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -4,7 +4,6 @@
 module core_decode
 (
 	input  word        insn,
-	input  psr_flags   flags,
 
 	output insn_decode dec
 );
@@ -51,17 +50,6 @@ module core_decode
 	//TODO
 	logic restore_spsr;
 
-	logic cond_undefined, cond_execute, explicit_cond;
-
-	core_decode_conds conds
-	(
-		.cond(insn `FIELD_COND),
-		.execute(cond_execute),
-		.undefined(cond_undefined),
-		.conditional(explicit_cond),
-		.*
-	);
-
 	logic snd_is_imm, snd_ror_if_imm, snd_shift_by_reg_if_reg, snd_undefined;
 	snd_decode snd;
 
diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv
index 643c942..ebcc098 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/decode/mux.sv
@@ -5,10 +5,6 @@ module core_decode_mux
 (
 	input  word          insn,
 
-	input  logic         cond_undefined,
-	                     cond_execute,
-	                     explicit_cond,
-
 	input  logic         branch_link,
 
 	input  snd_decode    snd,
@@ -74,10 +70,10 @@ module core_decode_mux
 		ldst = 0;
 		branch = 0;
 		coproc = 0;
-		execute = cond_execute;
-		undefined = cond_undefined;
+		execute = 1;
+		undefined = 0;
 		writeback = 0;
-		conditional = explicit_cond;
+		conditional = 0;
 		restore_spsr = 0;
 
 		spsr = 0;
@@ -139,8 +135,8 @@ module core_decode_mux
 				update_flags = data_update_flags;
 				restore_spsr = data_restore_spsr;
 
-				undefined = undefined | snd_undefined;
-				conditional = conditional | data_conditional;
+				undefined = snd_undefined;
+				conditional = data_conditional;
 			end
 
 			`GROUP_LDST_SINGLE_IMM, `GROUP_LDST_SINGLE_REG: begin
@@ -152,7 +148,7 @@ module core_decode_mux
 				dec_ldst = ldst_single;
 				ldst_addr = ldst_single;
 
-				undefined = undefined | snd_undefined;
+				undefined = snd_undefined;
 			end
 
 			`GROUP_LDST_MISC_IMM, `GROUP_LDST_MISC_REG:
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index d938699..bb52443 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -6,29 +6,29 @@ module core_fetch
 	input  logic clk,
 	             stall,
 	             branch,
-	             flush,
 	             fetched,
 	             wr_pc,
+	             prefetch_flush,
 	input  ptr   branch_target,
 	input  word  wr_current,
 	             fetch_data,
 
 	output logic fetch,
+	             flush,
 	output word  insn,
 	output ptr   insn_pc,
 	             addr
 );
 
 	ptr next_pc, head, hold_addr, target;
-	logic fetched_valid, do_flush, discard;
+	logic fetched_valid, discard;
 
+	assign flush = branch || prefetch_flush;
 	assign target = wr_pc ? wr_current[31:2] : branch_target; //TODO: alignment exception
-	assign do_flush = branch || flush;
 	assign fetched_valid = fetched && !discard;
 
 	core_prefetch #(.ORDER(PREFETCH_ORDER)) prefetch
 	(
-		.flush(do_flush),
 		.fetched(fetched_valid),
 		.*
 	);
@@ -36,12 +36,12 @@ module core_fetch
 	always_comb begin
 		if(branch)
 			head = target;
-		else if(flush)
+		else if(prefetch_flush)
 			head = next_pc;
 		else
 			head = {30{1'bx}};
 
-		if(do_flush)
+		if(flush)
 			addr = head;
 		else if(fetch && fetched_valid)
 			addr = hold_addr + 1;
@@ -50,7 +50,7 @@ module core_fetch
 	end
 
 	always_ff @(posedge clk) begin
-		discard <= discard ? ~fetched : do_flush & fetch;
+		discard <= discard ? !fetched : flush && fetch;
 		hold_addr <= addr;
 	end
 
diff --git a/rtl/core/decode/conds.sv b/rtl/core/porch/conds.sv
index 60922a0..b8db1e7 100644
--- a/rtl/core/decode/conds.sv
+++ b/rtl/core/porch/conds.sv
@@ -1,9 +1,9 @@
 `include "core/decode/isa.sv"
 `include "core/uarch.sv"
 
-module core_decode_conds
+module core_porch_conds
 (
-	input  logic[3:0] cond,
+	input  word       insn,
 	input  psr_flags  flags,
 
 	output logic      execute,
@@ -15,7 +15,7 @@ module core_decode_conds
 		undefined = 0;
 		conditional = 1;
 
-		unique case(cond)
+		unique case(insn `FIELD_COND)
 			`COND_EQ: execute =  flags.z;
 			`COND_NE: execute = ~flags.z;
 			`COND_HS: execute =  flags.c;
diff --git a/rtl/core/porch/porch.sv b/rtl/core/porch/porch.sv
new file mode 100644
index 0000000..6f5caf7
--- /dev/null
+++ b/rtl/core/porch/porch.sv
@@ -0,0 +1,53 @@
+`include "core/uarch.sv"
+
+module core_porch
+(
+	input  logic       clk,
+	                   flush,
+	                   stall,
+	input  psr_flags   flags,
+
+	input  word        fetch_insn,
+	input  ptr         fetch_insn_pc,
+	input  insn_decode fetch_dec,
+
+	output word        insn,
+	output ptr         insn_pc,
+	output insn_decode dec
+);
+
+	logic execute, conditional, undefined;
+	insn_decode nop, hold_dec;
+
+	core_porch_conds conds
+	(
+		.*
+	);
+
+	assign nop.ctrl.execute = 0;
+	assign nop.ctrl.undefined = 0;
+	assign nop.ctrl.conditional = 0;
+
+	always_comb begin
+		dec = hold_dec;
+		dec.ctrl.execute = !flush && dec.ctrl.execute && execute;
+		dec.ctrl.undefined = !flush && (dec.ctrl.undefined || undefined);
+		dec.ctrl.conditional = !flush && (dec.ctrl.conditional || conditional);
+	end
+
+	always @(posedge clk)
+		if(!stall) begin
+			insn <= fetch_insn;
+			hold_dec <= fetch_dec;
+
+			if(!flush)
+				insn_pc <= fetch_insn_pc;
+		end
+
+	initial begin
+		insn = `NOP;
+		insn_pc = 0;
+		hold_dec = nop;
+	end
+
+endmodule