Rework bus architecture

4 files changed, 86 insertions, 54 deletions

diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv
index 6e29ac2..e4a76d2 100644
--- a/rtl/bus/master.sv
+++ b/rtl/bus/master.sv
@@ -20,41 +20,44 @@ module bus_master
 );
 
 	enum {
-		REQUEST,
-		WAIT,
-		RESPONSE
+		IDLE,
+		WAIT
 	} state;
 
 	assign data_rd = avl_readdata;
-	assign avl_byteenable = 4'b1111;
-
-	always_ff @(posedge clk) unique case(state)
-		REQUEST: if(start) begin
+	assign avl_byteenable = 4'b1111; //TODO
+
+	always_comb
+		unique case(state)
+			IDLE: ready = 0;
+			WAIT: ready = !avl_waitrequest;
+		endcase
+
+	always_ff @(posedge clk) begin
+		unique case(state)
+			IDLE: begin
+				avl_read <= 0;
+				avl_write <= 0;
+			end
+
+			WAIT:
+				if(!start)
+					state <= IDLE;
+		endcase
+
+		if(!avl_waitrequest && start) begin
 			avl_address <= {addr, 2'b00};
 			avl_read <= ~write;
 			avl_write <= write;
 			avl_writedata <= data_wr;
 			state <= WAIT;
 		end
-
-		WAIT: if(~avl_waitrequest) begin
-			ready <= 1;
-			state <= RESPONSE;
-		end
-
-		RESPONSE: begin
-			ready <= 0;
-			avl_read <= 0;
-			avl_write <= 0;
-			state <= REQUEST;
-		end
-	endcase
+	end
 
 	initial begin
-		ready = 0;
+		state = IDLE;
 		avl_read = 0;
 		avl_write = 0;
-		state = REQUEST;
 	end
 
 endmodule
diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index a57c679..e8c6a9b 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -17,7 +17,7 @@ module core_fetch
 	             addr
 );
 
-	ptr next_pc, head;
+	ptr next_pc, head, hold_addr;
 	logic fetched_valid, do_flush, discard;
 
 	assign do_flush = branch | flush;
@@ -30,7 +30,7 @@ module core_fetch
 		.*
 	);
 
-	always_comb
+	always_comb begin
 		if(branch)
 			head = target;
 		else if(flush)
@@ -38,17 +38,21 @@ module core_fetch
 		else
 			head = {30{1'bx}};
 
-	always_ff @(posedge clk) begin
 		if(do_flush)
-			addr <= head;
+			addr = head;
 		else if(fetched_valid)
-			addr <= addr + 1;
+			addr = hold_addr + 1;
+		else
+			addr = hold_addr;
+	end
 
+	always_ff @(posedge clk) begin
 		discard <= discard ? ~fetched : do_flush & fetch;
+		hold_addr <= addr;
 	end
 
 	initial begin
-		addr = 0;
+		hold_addr = 0;
 		discard = 0;
 	end
 
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index 486ec96..4025339 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -23,19 +23,16 @@ module core_prefetch
 
 	assign insn = flush ? `NOP : prefetch[0];
 	assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
-
-	always_comb
-		if((valid == SIZE - 2) & fetched)
-			fetch = 0;
-		else
-			fetch = ~&valid;
+	assign fetch = !stall || ~&valid;
 
 	always_ff @(posedge clk) begin
 		insn_pc <= flush ? head : next_pc;
 
-		if(~flush & fetched & (valid == SIZE - 1))
+		if(flush)
+			prefetch[SIZE - 1] <= `NOP;
+		else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall})
 			prefetch[SIZE - 1] <= fetch_data;
-		else
+		else if(!stall)
 			prefetch[SIZE - 1] <= `NOP;
 
 		if(flush)
diff --git a/rtl/core/mmu/mmu.sv b/rtl/core/mmu/mmu.sv
index 9d118c1..8d3b909 100644
--- a/rtl/core/mmu/mmu.sv
+++ b/rtl/core/mmu/mmu.sv
@@ -27,18 +27,26 @@ module core_mmu
 		DATA
 	} master, next_master;
 
+	logic active, hold_start, hold_write, hold_issue, hold_free, transition;
+	ptr hold_addr;
+	word hold_data_wr;
+
 	//TODO
 	assign insn_data_rd = bus_data_rd;
 	assign data_data_rd = bus_data_rd;
 
 	always_comb begin
 		next_master = master;
-		if(bus_ready) begin
-			if(insn_start)
-				next_master = INSN;
-			else if(data_start)
-				next_master = DATA;
-		end
+		if(bus_ready || !active)
+			unique case(master)
+				DATA: next_master = data_start ? DATA : INSN;
+				INSN: next_master = !data_start && !hold_start ? INSN : DATA;
+			endcase
+
+		// Causa UNOPTFLAT en Verilator con assign
+		transition = master != next_master;
+		hold_issue = transition && hold_start;
+		hold_free = transition || !hold_start;
 
 		insn_ready = 0;
 		data_ready = 0;
@@ -51,36 +59,56 @@ module core_mmu
 		unique case(next_master)
 			INSN: begin
 				bus_addr = insn_addr;
+				bus_write = 0;
+				bus_start = insn_start;
 				bus_data_wr = {32{1'bx}};
 			end
 
 			DATA: begin
 				bus_addr = data_addr;
+				bus_write = data_write;
+				bus_start = data_start;
 				bus_data_wr = data_data_wr;
 			end
 		endcase
+
+		if(hold_issue) begin
+			bus_addr = hold_addr;
+			bus_write = hold_write;
+			bus_start = 1;
+			bus_data_wr = hold_data_wr;
+		end
 	end
 
 	always @(posedge clk) begin
 		master <= next_master;
+		active <= bus_start || (active && !bus_ready);
 
-		unique case(next_master)
-			INSN: begin
-				bus_start <= insn_start;
-				bus_write <= 0;
-			end
+		if(hold_free)
+			unique case(next_master)
+				INSN: begin
+					hold_start <= data_start;
+					hold_addr <= data_addr;
+					hold_write <= data_write;
+					hold_data_wr <= data_data_wr;
+				end
 
-			DATA: begin
-				bus_start <= data_start;
-				bus_write <= data_write;
-			end
-		endcase
+				DATA: begin
+					hold_start <= insn_start;
+					hold_addr <= insn_addr;
+					hold_write <= 0;
+				end
+			endcase
 	end
 
 	initial begin
 		master = INSN;
-		bus_start = 0;
-		bus_write = 0;
+		active = 0;
+
+		hold_addr = 30'b0;
+		hold_start = 0;
+		hold_write = 0;
+		hold_data_wr = 0;
 	end
 
 endmodule