Add SDRAM test

1 files changed, 69 insertions, 19 deletions

diff --git a/rtl/conspiracion.sv b/rtl/conspiracion.sv
index 96c6fb8..83e7d10 100644
--- a/rtl/conspiracion.sv
+++ b/rtl/conspiracion.sv
@@ -1,29 +1,41 @@
 module conspiracion
 (
-	input  wire        clk_clk,            //    clk.clk
-	output wire [12:0] memory_mem_a,       // memory.mem_a
-	output wire [2:0]  memory_mem_ba,      //       .mem_ba
-	output wire        memory_mem_ck,      //       .mem_ck
-	output wire        memory_mem_ck_n,    //       .mem_ck_n
-	output wire        memory_mem_cke,     //       .mem_cke
-	output wire        memory_mem_cs_n,    //       .mem_cs_n
-	output wire        memory_mem_ras_n,   //       .mem_ras_n
-	output wire        memory_mem_cas_n,   //       .mem_cas_n
-	output wire        memory_mem_we_n,    //       .mem_we_n
-	output wire        memory_mem_reset_n, //       .mem_reset_n
-	inout  wire [7:0]  memory_mem_dq,      //       .mem_dq
-	inout  wire        memory_mem_dqs,     //       .mem_dqs
-	inout  wire        memory_mem_dqs_n,   //       .mem_dqs_n
-	output wire        memory_mem_odt,     //       .mem_odt
-	output wire        memory_mem_dm,      //       .mem_dm
-	input  wire        memory_oct_rzqin,   //       .oct_rzqin
-	input  wire        reset_reset_n       //  reset.reset_n
+	input  wire        clk_clk,
+	output wire [12:0] memory_mem_a,
+	output wire [2:0]  memory_mem_ba,
+	output wire        memory_mem_ck,
+	output wire        memory_mem_ck_n,
+	output wire        memory_mem_cke,
+	output wire        memory_mem_cs_n,
+	output wire        memory_mem_ras_n,
+	output wire        memory_mem_cas_n,
+	output wire        memory_mem_we_n,
+	output wire        memory_mem_reset_n,
+	inout  wire [7:0]  memory_mem_dq,
+	inout  wire        memory_mem_dqs,
+	inout  wire        memory_mem_dqs_n,
+	output wire        memory_mem_odt,
+	output wire        memory_mem_dm,
+	input  wire        memory_oct_rzqin,
+	input  wire        reset_reset_n,
+
+	input logic dir, clr, mov, add, io,
+	output logic[7:0] out,
+	output logic done
 );
 
+	enum {
+		IDLE,
+		IO,
+		RELEASE
+	} state;
+
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_rw;
 	logic ready, write, start;
 
+	logic [7:0] leds;
+
 	platform plat
 	(
 		.master_0_core_addr(addr),
@@ -35,6 +47,44 @@ module conspiracion
 		.*
 	);
 
-	initial start <= 0;
+	initial begin
+		addr <= 0;
+		start <= 0;
+		state <= IDLE;
+		done <= 0;
+	end
+
+	assign data_rw[7:0] = out;
+	assign write = dir;
+
+	always @(posedge clk_clk) unique case(state)
+		IDLE: begin
+			state <= RELEASE;
+
+			if(~clr)
+				out <= 0;
+			else if(~mov)
+				addr <= dir ? addr + 1 : addr - 1;
+			else if(~add)
+				out <= dir ? out + 1 : out - 1;
+			else if(~io) begin
+				start <= 1;
+				state <= IO;
+			end
+		end
+
+		IO: begin
+			done <= 1;
+			start <= 0;
+			if(ready) begin
+				if(~dir) out <= data_rd[7:0];
+				state <= RELEASE;
+			end
+		end
 
+		RELEASE: begin
+			done <= ~io;
+			if(clr & mov & add & io) state <= IDLE;
+		end
+	endcase
 endmodule