diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-10-27 05:02:31 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-27 05:55:04 -0600 |
| commit | a1135fc271f503bdc85508211c12201a38c646b8 (patch) | |
| tree | 241114055a5012b0053cf8ffe0c9b371c1db0ab0 /rtl | |
| parent | ebd3ef9b8ebe6c19d0965c3d5ee741c725180f85 (diff) | |
rtl/gfx: fix linear combiner
Diffstat (limited to '')
| -rw-r--r-- | rtl/gfx/gfx.sv | 4 | ||||
| -rw-r--r-- | rtl/gfx/horizontal_fold.sv | 2 | ||||
| -rw-r--r-- | rtl/gfx/mat_mat_mul.sv | 14 | ||||
| -rw-r--r-- | rtl/gfx/skid_flow.sv | 2 |
4 files changed, 14 insertions, 8 deletions
diff --git a/rtl/gfx/gfx.sv b/rtl/gfx/gfx.sv index 1974991..0d16552 100644 --- a/rtl/gfx/gfx.sv +++ b/rtl/gfx/gfx.sv @@ -44,9 +44,9 @@ module gfx always_ff @(posedge clk) begin if (cmd_write) begin if (cmd_address[4]) - a[cmd_address[3:2]][cmd_address[1:0]] <= writedata; - else b[cmd_address[3:2]][cmd_address[1:0]] <= writedata; + else + a[cmd_address[3:2]][cmd_address[1:0]] <= writedata; end if (done) diff --git a/rtl/gfx/horizontal_fold.sv b/rtl/gfx/horizontal_fold.sv index ee56098..f244b55 100644 --- a/rtl/gfx/horizontal_fold.sv +++ b/rtl/gfx/horizontal_fold.sv @@ -44,7 +44,7 @@ module horizontal_fold genvar i; generate - for (i = 1; i < `FLOATS_PER_VEC; ++i) begin: stages + for (i = 1; i < `FP_ADD_STAGES; ++i) begin: stages always_ff @(posedge clk) if (!stall) queued[i] <= queued[i - 1]; diff --git a/rtl/gfx/mat_mat_mul.sv b/rtl/gfx/mat_mat_mul.sv index 7c21249..85ff7d6 100644 --- a/rtl/gfx/mat_mat_mul.sv +++ b/rtl/gfx/mat_mat_mul.sv @@ -15,7 +15,7 @@ module mat_mat_mul out_valid ); - mat4 a_hold, b_hold, b_transpose, q_hold, mul_b; + mat4 a_hold, b_hold, b_transpose, q_hold, q_transpose, mul_b; vec4 mul_q; logic mul_in_ready, mul_in_valid, mul_out_ready, mul_out_valid; index4 in_index, out_index; @@ -26,7 +26,7 @@ module mat_mat_mul assign mul_in_valid = in_valid || in_index != `INDEX4_MIN; assign mul_out_ready = out_ready || out_index != `INDEX4_MAX; - transpose transpose + transpose transpose_b ( .in(b), .out(b_transpose) @@ -44,12 +44,18 @@ module mat_mat_mul .* ); + transpose transpose_q + ( + .in(q_transpose), + .out(q) + ); + always_comb begin mul_b = b_hold; mul_b[0] = b_transpose[0]; - q = q_hold; - q[`VECS_PER_MAT - 1] = mul_q; + q_transpose = q_hold; + q_transpose[`VECS_PER_MAT - 1] = mul_q; end always_ff @(posedge clk or negedge rst_n) diff --git a/rtl/gfx/skid_flow.sv b/rtl/gfx/skid_flow.sv index a38df65..2b521e5 100644 --- a/rtl/gfx/skid_flow.sv +++ b/rtl/gfx/skid_flow.sv @@ -15,7 +15,7 @@ module skid_flow assign stall = !in_ready; assign in_ready = was_ready || !was_valid; - assign out_valid = in_valid || was_valid; + assign out_valid = in_valid || stall; always @(posedge clk or negedge rst_n) if (!rst_n) begin |