Rewrite duplicate ldst logic as signal ldst_next

5 files changed, 20 insertions, 16 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index d204b96..506af2b 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -87,7 +87,7 @@ module core_control
 	);
 
 	word mem_offset;
-	logic ldst, ldst_writeback, pop_valid;
+	logic ldst, ldst_next, ldst_writeback, pop_valid;
 	reg_num popped;
 
 	core_control_ldst ctrl_ldst
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index 049cf0e..6a7ec15 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -16,6 +16,7 @@ module core_control_data
 	input  ctrl_cycle      cycle,
 	                       next_cycle,
 	input  ptr             pc,
+	input  logic           ldst_next,
 	input  word            mem_offset,
 	input  psr_flags       flags,
 
@@ -89,7 +90,7 @@ module core_control_data
 			c_in <= c_shifter;
 			saved_base <= q_shifter;
 		end else if(next_cycle.transfer) begin
-			if(!cycle.transfer || mem_ready)
+			if(ldst_next)
 				saved_base <= q_alu;
 		end else if(next_cycle.exception) begin
 			alu <= `ALU_ADD;
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index cc52864..12bd6b9 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -23,16 +23,18 @@ module core_control_ldst
 	                   mem_write,
 	                   pop_valid,
 	                   ldst,
+	                   ldst_next,
 	                   ldst_writeback,
 	output reg_num     popped
 );
 
-	logic ldst_pre, ldst_increment;
+	logic pre, increment;
 	reg_num popped_upper, popped_lower;
 	reg_list mem_regs, next_regs_upper, next_regs_lower;
 
+	assign popped = increment ? popped_lower : popped_upper;
+	assign ldst_next = !cycle.transfer || mem_ready;
 	assign mem_data_wr = rd_value_b;
-	assign popped = ldst_increment ? popped_lower : popped_upper;
 
 	core_control_ldst_pop pop
 	(
@@ -46,10 +48,10 @@ module core_control_ldst
 
 	always_ff @(posedge clk or negedge rst_n)
 		if(!rst_n) begin
+			pre <= 0;
 			ldst <= 0;
-			ldst_pre <= 0;
+			increment <= 0;
 			ldst_writeback <= 0;
-			ldst_increment <= 0;
 
 			mem_addr <= {$bits(mem_addr){1'b0}};
 			mem_regs <= {$bits(mem_regs){1'b0}};
@@ -60,13 +62,13 @@ module core_control_ldst
 			mem_start <= 0;
 
 			if(next_cycle.issue) begin
-				// TODO: dec.ldst.unprivileged/user_regs
+				// TODO: dec.ldst.unprivileged
 				// TODO: byte/halfword sizes
 				if(issue)
 					ldst <= dec.ctrl.ldst;
 
-				ldst_pre <= dec.ldst.pre_indexed;
-				ldst_increment <= dec.ldst.increment;
+				pre <= dec.ldst.pre_indexed;
+				increment <= dec.ldst.increment;
 				ldst_writeback <= dec.ldst.writeback;
 
 				mem_regs <= dec.ldst.regs;
@@ -77,9 +79,9 @@ module core_control_ldst
 					mem_offset <= alu_b;
 				end
 
-				if(!cycle.transfer || mem_ready) begin
-					mem_regs <= ldst_increment ? next_regs_lower : next_regs_upper;
-					mem_addr <= ldst_pre ? q_alu[31:2] : alu_a[31:2];
+				if(ldst_next) begin
+					mem_regs <= increment ? next_regs_lower : next_regs_upper;
+					mem_addr <= pre ? q_alu[31:2] : alu_a[31:2];
 				end
 
 				mem_start <= !cycle.transfer || (mem_ready && pop_valid);
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index ee63b42..3cc0ca5 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -7,10 +7,10 @@ module core_control_select
 
 	input  insn_decode dec,
 
-	input  ctrl_cycle  cycle,
-	                   next_cycle,
+	input  ctrl_cycle  next_cycle,
 	input  logic       mem_ready,
 	                   pop_valid,
+	                   ldst_next,
 	input  reg_num     popped,
 	                   final_rd,
 	                   mul_r_add_lo,
@@ -33,7 +33,7 @@ module core_control_select
 			ra = dec.data.rn;
 			rb = dec.snd.r;
 		end else if(next_cycle.transfer) begin
-			if(!cycle.transfer || mem_ready)
+			if(ldst_next)
 				// final_rd viene de dec.ldst.rd
 				rb = pop_valid ? popped : final_rd;
 		end else if(next_cycle.mul_acc_ld) begin
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index a85956f..914236c 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -23,6 +23,7 @@ module core_control_writeback
 	                   mul_r_add_hi,
 	input  logic       issue,
 	                   pop_valid,
+	                   ldst_next,
 
 	output reg_num     rd,
 	                   final_rd,
@@ -97,7 +98,7 @@ module core_control_writeback
 			if(next_cycle.issue)
 				final_rd <= dec.data.rd;
 			else if(next_cycle.transfer) begin
-				if((!cycle.transfer || mem_ready) && pop_valid)
+				if(ldst_next && pop_valid)
 					final_rd <= popped;
 			end else if(next_cycle.base_writeback)
 				final_rd <= ra;