Implement breakpoints

9 files changed, 28 insertions, 5 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 89a2a68..05bce76 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -14,7 +14,9 @@ module arm810
 	input  word       bus_data_rd,
 	output word       bus_data_wr,
 	output logic[3:0] bus_data_be,
-	output logic      halted
+
+	output logic      halted,
+	                  breakpoint
 );
 
 	ptr fetch_insn_pc, fetch_head, insn_addr;
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 9f398dc..92e27d6 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -32,6 +32,7 @@ module core_control
 	                       stall,
 	                       branch,
 	                       writeback,
+	                       breakpoint,
 	                       update_flags,
 	                       c_in,
 	output reg_num         rd,
diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index ffdf250..b8cf3ff 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -18,6 +18,7 @@ module core_control_issue
 
 	output logic       issue,
 	                   undefined,
+	                   breakpoint,
 	output ptr         pc,
 	                   pc_visible,
 	                   next_pc_visible
@@ -27,6 +28,7 @@ module core_control_issue
 
 	assign valid = !next_bubble && !halt;
 	assign issue = next_cycle.issue && dec.ctrl.execute && valid;
+	assign breakpoint = issue && dec.ctrl.bkpt;
 	assign next_pc_visible = insn_pc + 2;
 
 	always_ff @(posedge clk or negedge rst_n)
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index 085f11e..f42dcf0 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -24,7 +24,7 @@ module core_control_stall
 	logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, psr_hazard, flags_hazard;
 
 	assign stall = !next_cycle.issue || next_bubble || halt;
-	assign halted = halt && !next_bubble;
+	assign halted = halt && !next_bubble && next_cycle.issue;
 	assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard || psr_hazard;
 
 	//FIXME: pc_rd_hazard no debería definirse sin final_writeback?
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index f16db9a..6534897 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -29,6 +29,7 @@ module core_decode
 	assign dec_ctrl.mul = mul;
 	assign dec_ctrl.psr = psr;
 	assign dec_ctrl.ldst = ldst;
+	assign dec_ctrl.bkpt = bkpt;
 	assign dec_ctrl.branch = branch;
 	assign dec_ctrl.coproc = coproc;
 	assign dec_ctrl.execute = execute;
@@ -44,8 +45,8 @@ module core_decode
 	assign dec_psr.restore_spsr = restore_spsr;
 
 	logic execute, undefined, conditional, writeback, update_flags,
-	      restore_spsr, branch, ldst, mul, psr, coproc, psr_saved,
-	      psr_write, psr_wr_flags, psr_wr_control;
+	      restore_spsr, branch, ldst, mul, psr, coproc, bkpt,
+	      psr_saved, psr_write, psr_wr_flags, psr_wr_control;
 
 	core_decode_mux mux
 	(
diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv
index 7c27f49..4c9f316 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -209,4 +209,8 @@
 
 `define FIELD_SWI_IMM [23:0]
 
+// GDB swbreak (a magic 'und')
+
+`define INSN_GDB_SWBREAK 28'h7ffdefe 
+
 `endif
diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv
index 3f613a4..f05b711 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/decode/mux.sv
@@ -57,6 +57,7 @@ module core_decode_mux
 	                     mul,
 	                     psr,
 	                     coproc,
+	                     bkpt,
 	                     psr_saved,
 	                     psr_write,
 	                     psr_wr_flags,
@@ -71,6 +72,7 @@ module core_decode_mux
 	always_comb begin
 		mul = 0;
 		ldst = 0;
+		bkpt = 0;
 		branch = 0;
 		coproc = 0;
 		execute = 1;
@@ -230,6 +232,14 @@ module core_decode_mux
 				writeback = 1;
 			end
 
+`ifdef VERILATOR
+			// No es parte de ARM del todo, es un hack para soportar gdb
+			`INSN_GDB_SWBREAK: begin
+				bkpt = 1;
+				dec_data.uses_rn = 0;
+			end
+`endif
+
 			default:
 				undefined = 1;
 		endcase
@@ -252,6 +262,7 @@ module core_decode_mux
 
 			mul = 1'bx;
 			psr = 1'bx;
+			bkpt = 1'bx;
 			ldst = 1'bx;
 			branch = 1'bx;
 			coproc = 1'bx;
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv
index c1e5abb..ac3b567 100644
--- a/rtl/core/uarch.sv
+++ b/rtl/core/uarch.sv
@@ -87,7 +87,8 @@ typedef struct packed
 	      coproc,
 	      ldst,
 	      mul,
-	      psr;
+	      psr,
+	      bkpt;
 } ctrl_decode;
 
 typedef struct packed
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 84b875e..507a74c 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -4,6 +4,7 @@ module conspiracion
 	input  wire        rst_n,
 	input  wire        halt,
 	output wire        cpu_halted,
+	output wire        breakpoint,
 	output wire [12:0] memory_mem_a,
 	output wire [2:0]  memory_mem_ba,
 	output wire        memory_mem_ck,