Add bus master forward signals: irq, cpu_clk

2 files changed, 10 insertions, 2 deletions

diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index e4a76d2..560cb67 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -9,6 +9,8 @@ module bus_master
 	output logic       ready,
 	output logic[31:0] data_rd,
 	input  logic[31:0] data_wr,
+	output logic       cpu_clk,
+	                   irq,
 
 	output logic[31:0] avl_address,
 	output logic       avl_read,
@@ -16,7 +18,8 @@ module bus_master
 	input  logic[31:0] avl_readdata,
 	output logic[31:0] avl_writedata,
 	input  logic       avl_waitrequest,
-	output logic[3:0]  avl_byteenable
+	output logic[3:0]  avl_byteenable,
+	input  logic       avl_irq
 );
 
 	enum {
@@ -24,6 +27,9 @@ module bus_master
 		WAIT
 	} state;
 
+	assign irq = avl_irq;
+	assign cpu_clk = clk;
+
 	assign data_rd = avl_readdata;
 	assign avl_byteenable = 4'b1111; //TODO
 
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 940e46a..41b614f 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -35,7 +35,7 @@ module conspiracion
 
 	logic[29:0] addr;
 	logic[31:0] data_rd, data_wr;
-	logic clk_core, ready, write, start;
+	logic cpu_clk, ready, write, start, irq;
 
 	arm810 core
 	(
@@ -53,12 +53,14 @@ module conspiracion
 
 	platform plat
 	(
+		.master_0_core_cpu_clk(cpu_clk),
 		.master_0_core_addr(addr),
 		.master_0_core_data_rd(data_rd),
 		.master_0_core_data_wr(data_wr),
 		.master_0_core_ready(ready),
 		.master_0_core_write(write),
 		.master_0_core_start(start),
+		.master_0_core_irq(irq),
 		.pll_0_outclk3_clk(),
 		.pio_0_external_connection_export(),
 		.*