diff options
| author | Alejandro Soto <alejandro@34project.org> | 2024-05-16 01:08:04 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2024-05-24 05:58:19 -0600 |
| commit | b21c321a059e11edeece1c90d97776bb0716d7a0 (patch) | |
| tree | cb7c3e6c2a5f6fd153c3b01d61040a2c901e0ba8 /rtl/wb2axip/axis2mm.v | |
| parent | a6c23ba92d0c2cad9862de1cb11c19b4e06fc0e6 (diff) | |
rtl: fix quartus errors: parser, synthesis, fitter
Diffstat (limited to '')
| -rw-r--r-- | rtl/wb2axip/axis2mm.v | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/rtl/wb2axip/axis2mm.v b/rtl/wb2axip/axis2mm.v index d578e41..90c6d7d 100644 --- a/rtl/wb2axip/axis2mm.v +++ b/rtl/wb2axip/axis2mm.v @@ -208,7 +208,7 @@ //////////////////////////////////////////////////////////////////////////////// // // -`default_nettype none +//`default_nettype none // }}} module axis2mm #( // {{{ @@ -272,7 +272,7 @@ module axis2mm #( // addresses. Only applies to non fixed addresses and // (possibly) non-continuous bursts. (THIS IS A PLACEHOLDER. // UNALIGNED ADDRESSING IS NOT CURRENTLY SUPPORTED.) - localparam [0:0] OPT_UNALIGNED = 0, + /*local*/parameter [0:0] OPT_UNALIGNED = 0, // parameter [0:0] OPT_LOWPOWER = 1'b0, parameter [0:0] OPT_CLKGATE = OPT_LOWPOWER, @@ -288,8 +288,8 @@ module axis2mm #( // Size of the AXI-lite bus. These are fixed, since 1) AXI-lite // is fixed at a width of 32-bits by Xilinx def'n, and 2) since // we only ever have 4 configuration words. - localparam C_AXIL_ADDR_WIDTH = 5, - localparam C_AXIL_DATA_WIDTH = 32 + /*local*/parameter C_AXIL_ADDR_WIDTH = 5, + /*local*/parameter C_AXIL_DATA_WIDTH = 32 // }}} ) ( // {{{ @@ -2230,5 +2230,5 @@ module axis2mm #( // }}} endmodule `ifndef YOSYS -`default_nettype wire +//`default_nettype wire `endif |